Pipeline Hazards: When One Instruction Depends on Another’s Result
In a pipelined CPU, an instruction pipeline hazard occurs when the next instruction cannot proceed through the pipeline as expected because of a constraint (timing/resource/data/control). The specific case “an instruction depends on the result of a previous instruction” corresponds to a keyword data hazard—most commonly characterized as a keyword RAW (read-after-write) hazard.
In the given options, the correct choice is:
- (ii) Data hazard
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Quick classification of the other options
A keyword structural hazard happens when pipeline stages can’t use the required hardware simultaneously (e.g., one memory port shared by instruction fetch and data access).
A keyword syntax hazard is not a standard pipeline hazard category in classical pipeline-hazard models.
A keyword memory hazard is not the standard named category for “depends on previous result” in the standard structural/data/control hazard framework.
How a Data Hazard Arises (Classic Case)
- 1Step 1
Instruction needs a value produced by instruction (e.g., same register).
- 2Step 2
produces the value in a later pipeline stage than needs it.
- 3Step 3
Use stalling (pipeline interlock) or forwarding/bypassing to provide the value early.
- 4Step 4
The pipeline proceeds correctly only because the hazard is managed—this is the essence of a keyword data hazard.
Rule of Thumb
If the issue is about values/operands being needed too early, it’s a data hazard. If it’s about hardware being unavailable, it’s a structural hazard.
About “Syntax hazard” and “Memory hazard” options
In many standard textbooks, pipeline hazards are grouped into structural, data, and control hazards. “Syntax hazard” is not a typical pipeline hazard category, and “memory hazard” is not the standard label for the specific dependency case you described.
| Option | Meaning in pipeline-hazard terms | Likely correct for “depends on previous result”? |
|---|---|---|
| (i) Structural hazard | Resource conflict between stages | No |
| (ii) Data hazard | Register/memory value dependency timing | Yes |
| (iii) Syntax hazard | Ill-formed instruction/program syntax | No (not a standard pipeline hazard category) |
| (iv) Memory hazard | Memory system ordering/timing issues | Not the standard label for this dependency question |
Which Hazard Fits the Dependency Case?
Qualitative match to the scenario “depends on previous instruction result”.
Typical Resolution of a Data Hazard in a Pipeline
Operand not ready
Cycle when $I_2$ needs operandA value produced by is not yet available in the stage where requires it."
Forward or stall
Next decisionForwarding may supply the value; otherwise interlocking stalls ."
Correct execution
After resolutionPipeline continues with the correct operand value."
Pipeline Hazard Quick-Check
Knowledge Check
Which pipeline hazard occurs when an instruction depends on the result of a previous instruction?