Hazards in Pipeline Architecture: Types, Causes, and Examples
Pipeline architecture improves throughput by overlapping instruction execution stages. However, overlapping can cause incorrect results or reduced performance due to pipeline hazards—commonly classified as data hazards , control hazards , and structural hazards.
Mermaid overview of the three classic hazard types:
Note: Most textbook treatments of hazards focus on in-order scalar pipelines, where RAW (Read After Write) is the dominant data hazard category.
Pipeline Hazards (Data, Control, Structural) in Computer Architecture (Tutorial)
Key pipeline terms (quick learning)
- pipeline stage: e.g., IF, ID, EX, MEM, WB
- program counter (PC)
- instruction fetch (IF)
These are the entities that hazards tend to disrupt: register availability (data hazards), PC update (control hazards), and shared units/memory ports (structural hazards).
1) Data Hazards (Dependence on Unready Results)
What they are
A data hazard occurs when an instruction needs an operand that previous instructions have not produced yet (or will overwrite later). In classic pipelines, the most important form is RAW.
RAW example (dependence)
Assume a 5-stage pipeline (IF, ID, EX, MEM, WB) and an arithmetic instruction producing a register value:
- I1:
ADD R1, R2, R3 - I2:
SUB R4, R1, R5(needs R1 as an input)
If I2 reaches the stage that reads registers before I1 reaches the stage that writes back R1, I2 may read the old value of R1 (incorrect behavior).
Mermaid timeline (simplified):
How data hazards are handled
Common mitigation mechanisms:
- forwarding/bypassing
- stall (pipeline bubble)
- instruction scheduling
Tip: Many problems reduce to “Where does the producer’s value become available?”
If the value is available after EX, forwarding can avoid stalls; if it’s available only after MEM (e.g., loads), stalls may be needed.
Diagnosing a Data Hazard (RAW) in a Pipeline
- 1Step 1
Find which source registers the later instruction reads and which destination registers the earlier instruction writes.
- 2Step 2
Track when the producer computes the value (EX), accesses memory (MEM), and updates the register file (WB).
- 3Step 3
Typically, the consumer’s operand is needed at its EX stage (after register read in ID).
- 4Step 4
If the consumer’s needed time occurs before the producer’s value is available (or before forwarding can supply it), a data hazard exists.
- 5Step 5
Use forwarding if the value can be routed; otherwise insert stalls or schedule independent instructions.
Forwarding vs Stalling
If the producer’s result is available early enough, forwarding resolves the RAW hazard without reducing throughput. If the result is only available later (common with load-use), a stall (bubble) may be unavoidable.
Not All “Dependencies” Are Hazards in In-Order Pipelines
In-order pipelines typically care most about RAW hazards because the pipeline order prevents some reorder anomalies. WAR/WAW are more central in out-of-order or register-renaming contexts.
2) Control Hazards (Uncertain Next PC due to Branches/Jumps)
What they are
Control hazard occurs because the pipeline must fetch instructions before it knows whether a branch is taken and what the target address is.
There are two classic subtypes:
- branch direction uncertainty
- branch target uncertainty
Example: Branch decision delay
Consider:
- I1:
BEQ R1, R2, Label(branch depends on R1 and R2) - I2: instruction immediately after branch in sequential order (fetched while outcome unknown)
- I3: instructions at the Label target (might be correct if branch taken)
If the pipeline fetches I2 before knowing the branch outcome, and the branch is taken, I2 is wrong and must be discarded (flush), wasting cycles.
Mermaid conceptual flow:
Mitigation approaches
- pipeline flush
- branch prediction
- speculative execution
- delayed branching
Typical Control Hazard Flow (Branch Taken)
IF: fetch branch
t0Pipeline begins fetching the conditional branch instruction."
IF/ID: fetch sequential next instruction
t1Next instruction is fetched speculatively because target/outcome isn't resolved yet."
EX: evaluate condition
t2+When the condition resolves, pipeline knows whether branch is taken."
PC redirect + flush if needed
t3If taken, wrong-path instructions are flushed and correct path begins."
3) Structural Hazards (Resource Conflicts)
What they are
A structural hazard occurs when the hardware cannot support all simultaneous stage requirements.
Classic example: a single memory used for both instruction fetch and data access.
- Stage IF needs to read instruction memory.
- Stage MEM for a load/store needs to access data memory. If both must happen in the same cycle and there is only one memory port, a conflict arises.
Example scenario (single-ported memory)
Assume:
- I1 is a load:
LW R1, 0(R2)(uses MEM stage for data) - I2 is the next instruction to be fetched (uses IF stage)
In a given cycle:
- IF tries to fetch I2
- MEM tries to read data for I1
If there is only one shared memory port and no replication/porting, the pipeline must stall some stage, reducing throughput.
Mitigation:
- separate instruction and data memories (Harvard-style)
- multi-ported caches
- stalling
Putting It Together: Concrete Instruction Sequences
(A) Data hazard (RAW) example
Instruction stream:
ADD R1, R2, R3SUB R4, R1, R5
Outcome without forwarding/stall: SUB reads old R1 → incorrect result.
With forwarding: SUB receives R1 directly from producer path → correct result.
(B) Control hazard example (branch)
Instruction stream:
BEQ R1, R2, LabelADD R3, R3, #1(sequential)Label: SUB R4, R4, #1
If branch is taken, instruction 2 is fetched but should be flushed.
If branch is not taken, instruction 2 is correct.
(C) Structural hazard example (resource conflict)
Instruction stream (conceptual):
LW R1, 0(R2)(needs MEM access)AND R3, R4, R5(needs IF fetch)
If instruction and data share a single memory port, one of these overlapped operations must stall.
Where Hazards Manifest in a 5-Stage Pipeline (High-Level)
Qualitative mapping of hazard likelihood to stages; actual behavior depends on ISA and microarchitecture.
Common Edge Cases and Clarifications
Knowledge Check
In a classic in-order pipelined processor, which hazard is most directly associated with a later instruction reading a register before an earlier instruction writes it?