Performance Impacts in Pipelined Processors: Stage Delays, Dependencies, and Shared Resources

A pipelined processor aims to increase throughput by overlapping the execution of multiple instructions across pipeline stages. However, pipeline performance is sensitive to (i) unequal stage delays, (ii) instruction-to-instruction dependencies, and (iii) conflicts over shared hardware resources. When these issues occur, the effective throughput drops because the pipeline either must run at a slower clock (due to the slowest stage) or inserts bubbles (stalls) to resolve hazards. Therefore, the correct choice among the listed statements is: (iv) All of these.

Performance metrics used in pipelining

• Pipeline throughput: affected by stall cycles and clock frequency.
• Clock period: increases when stage delays are unequal.
• CPI: increases when stalls/bubbles occur.
• Pipeline hazard: includes data, control, and structural hazards.

Note: The question asks which of the options causes performance suffering. Each of the listed mechanisms is a known cause of reduced pipeline performance (throughput) in real designs.

(i) Unequal pipeline-stage delays reduce performance

For a synchronous pipelined design, the Pipeline clock period must be long enough to accommodate the maximum combinational delay among stages (including setup time and clock skew). If one stage is slower, it dictates a larger clock period, $T_{clk}$, which reduces maximum throughput even when there are no hazards.

Key idea

If stage delays are $d_1, d_2, \dots, d_k$, then:

• $T_{clk} \ge \max(d_1, d_2, \dots, d_k)$
• Pipeline throughput (ideal) is roughly proportional to $1/T_{clk}$

Thus, different stage delays lead to a slower clock, lowering throughput.

(ii) Consecutive dependent instructions reduce performance

When Data dependency exists between consecutive instructions, the pipeline may face a Data hazard.

Common forms:

• RAW (read-after-write): instruction $I_{n+1}$ needs a register value that $I_n$ hasn’t produced yet.
• Without mitigation, the pipeline must stall: it inserts bubbles until the required value is available in the needed stage.
• With mitigation, techniques like Forwarding can reduce stalls, but not all hazards are eliminated (e.g., some load-use patterns or control hazards still require bubbles).

Quantitative intuition

Let:

• $N$ = number of instructions
• $S$ = number of stall cycles inserted Then effective:
• $CPI \approx CPI_{ideal} + \frac{S}{N}$

So, instruction dependencies increase CPI, which reduces throughput.

(iii) Shared hardware resources create structural hazards

If multiple pipeline stages need the same hardware at the same time, the design can’t simultaneously serve all requests. This is the classic Structural hazard.

Example conflict

• If a processor uses a single Memory port for both instruction fetch and data load/store, then during some cycle both may require memory access.
• When both requests target the same resource and there is no replication/buffering, the pipeline must stall one of the stages (insert bubbles).

Performance implication

Structural hazards increase the number of stall cycles, which:

• increases $CPI$
• reduces effective throughput

So, hardware resource sharing can directly limit overlap between instructions.

(iv) Therefore: All of these

Each option (i)–(iii) causes performance suffering in a pipelined processor:

• (i) Different stage delays → larger required clock period → lower throughput.
• (ii) Dependent consecutive instructions → data hazards → stalls → higher CPI.
• (iii) Shared hardware resources → structural hazards → stalls → higher CPI.

Hence the correct selection is (iv) All of these.