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Pipeline Throughput Increase from Replacing a Stage in a Four-Stage Pipeline

Pipeline Throughput Increase from Replacing a Stage in a Four-Stage Pipeline

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Nov 4, 2026

In an ideal synchronous pipeline, the clock period is set by the slowest (maximum-delay) pipeline stage, because all stages must complete before the next clock edge. This makes the pipeline throughput proportional to the clock frequency f=1Tclkf = \frac{1}{T_{\text{clk}}}. In symbols, Tclk=max⁡i(ti)T_{\text{clk}} = \max_i (t_i) for stage delays tit_i.
So, replacing one stage with a functionally equivalent design changes the pipeline’s throughput by changing the maximum stage delay (the bottleneck).

Key terms:

  • pipeline throughput
  • clock period
  • pipeline bottleneck
  • pipeline stage delay

Pipeline Throughput & Clock Period (Bottleneck Stage) Explained

Compute the original and new pipeline throughput and percentage increase

  1. 1
    Step 1

    For stage delays 800, 500, 400, 300 ps, the clock period is the maximum delay: Told=max⁡(800,500,400,300)=800 ps.T_{\text{old}} = \max(800,500,400,300) = 800\text{ ps}.

  2. 2
    Step 2

    Throughput is proportional to frequency: fold=1Told=1800 ps.f_{\text{old}} = \frac{1}{T_{\text{old}}} = \frac{1}{800\text{ ps}}.

  3. 3
    Step 3

    The 800-ps stage is replaced by two stages with delays 600 and 350 ps. The pipeline now contains delays 600, 350, 500, 400, 300 ps, so Tnew=max⁡(600,350,500,400,300)=600 ps.T_{\text{new}} = \max(600,350,500,400,300) = 600\text{ ps}.

  4. 4
    Step 4

    New frequency: fnew=1Tnew=1600 ps.f_{\text{new}} = \frac{1}{T_{\text{new}}} = \frac{1}{600\text{ ps}}.

  5. 5
    Step 5

    Percentage increase: %Δ=fnew−foldfold×100=(1/600−1/8001/800)×100.\%\Delta = \frac{f_{\text{new}}-f_{\text{old}}}{f_{\text{old}}}\times 100 = \left(\frac{1/600-1/800}{1/800}\right)\times 100. Simplify: 1/600−1/8001/800=800600−1=43−1=13.\frac{1/600-1/800}{1/800}=\frac{800}{600}-1=\frac{4}{3}-1=\frac{1}{3}. Therefore, %Δ=13×100≈33.33%.\%\Delta = \frac{1}{3}\times 100 \approx 33.33\%.

How to spot the bottleneck quickly

The achievable clock period equals the maximum stage delay. So you only need to compare stage delays before vs. after replacement to see the throughput change.

Assumption being used

This calculation assumes an ideal synchronous pipeline where stage overlap is perfect and the clock is limited only by combinational delay (no extra pipeline-register overhead or hazards).

Bottleneck stage delay before vs. after replacement

Pipeline clock period follows the maximum stage delay.

Common pitfalls and related concepts

Pipeline Throughput Quick Checks

1 / 4
Question · Term

Pipeline clock period in an ideal synchronous pipeline equals what?

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Answer · Definition

Tclk=max⁡i(ti)T_{\text{clk}} = \max_i(t_i) (the slowest stage delay).

Knowledge Check

Question 1 of 4
Q1Single choice

The original four-stage pipeline has stage delays 800, 500, 400, 300 ps. What is the pipeline clock period (ideal synchronous case)?

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