One-, Two-, and Three-Address Instructions: Definitions, Formats, and Examples

One-, Two-, and Three-Address Instructions: Definitions, Formats, and Examples

Verified Sources
Nov 4, 2026

In instruction-set design and compiler back-end code generation, Address field count is often used to classify intermediate-code and assembly-like formats into one-address , two-address , and three-address forms.

A key idea: the “address” count usually refers to how many operand locations are explicitly referenced in the instruction word(s), not to the number of arithmetic inputs in the abstract computation. For example, a three-address instruction like “Rd←Rs1 op Rs2R_d \leftarrow R_s1 \ \text{op}\ R_s2” explicitly names two sources and a destination. Meanwhile, one-address architectures typically rely on an accumulator or implicit registers so that fewer operands appear in the instruction.

This section gives clear formats, then works a single example expression through each style, and finally compares trade-offs in instruction length and register pressure using a small data visualization.

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Instruction Address Formats (One-/Two-/Three-Address) — Overview

Core mental model

Let the goal be to compute an expression such as:

X=A+BX = A + B

or a longer expression:

Y=(A+B)∗CY = (A + B) * C

Different address styles change how you encode operand locations:

  • One-address: uses an accumulator (or implicit operand registers). Many operations implicitly read from and/or write to the accumulator.
  • Two-address: uses two explicit addresses; commonly the second operand is overwritten with the result: op Rd,Rs⇒Rd←Rd op Rs\text{op } R_d, R_s \Rightarrow R_d \leftarrow R_d \ \text{op}\ R_s
  • Three-address: uses three explicit addresses: two sources and one destination: op Rd,Rs1,Rs2⇒Rd←Rs1 op Rs2\text{op } R_d, R_{s1}, R_{s2} \Rightarrow R_d \leftarrow R_{s1} \ \text{op}\ R_{s2}

Keywords for this section

  • accumulator
  • register operand
  • destination operand
  • source operand
  • register overwrite

One-Address Instructions

Typical format

In a classic “one-address” style, an arithmetic instruction names (at most) one explicit operand, while the other operand is implicit (usually the accumulator). A common model is:

ACC←ACC op MACC \leftarrow ACC \ \text{op}\ M

or:

  • Load: ACC←MACC \leftarrow M
  • Add from memory/register: ACC←ACC+MACC \leftarrow ACC + M

Example: compute X=A+BX = A + B

Assume memory locations/registers AA and BB, and an implicit accumulator ACCACC.

  1. Load AA into accumulator:
    • LOAD A
    • ACC←AACC \leftarrow A
  2. Add BB to accumulator:
    • ADD B
    • ACC←ACC+B=A+BACC \leftarrow ACC + B = A + B

Final result is left in the accumulator:

  • STORE X (optional, if the ISA requires explicit store)

Mini-instruction sequence

  • LOAD A
  • ADD B
  • STORE X

Two-Address Instructions

Typical format

Two-address forms name two operand addresses explicitly. A prevalent convention is that the destination is also one of the operands (often the first):

Rd←Rd op RsR_d \leftarrow R_d \ \text{op}\ R_s

So the instruction overwrites one input location with the result.

Example: compute X=A+BX = A + B

Using registers R1R1 for AA and R2R2 for BB:

  1. Copy/prepare destination register:
    • MOV R1, A (or load AA into destination)
  2. Perform operation with overwrite:
    • ADD R1, B means R1←R1+BR1 \leftarrow R1 + B
  3. Store result:
    • MOV X, R1 (or STORE X, R1)

Result: X=A+BX = A + B.

What changed vs one-address?

  • The accumulator is no longer the only implicit place.
  • You explicitly name both an operand that is overwritten and another operand that is read.

Three-Address Instructions

Typical format

Three-address instructions explicitly name:

  • two source operands and
  • one destination operand.

A standard arithmetic encoding is:

Rd←Rs1 op Rs2R_d \leftarrow R_{s1} \ \text{op}\ R_{s2}

Example: compute X=A+BX = A + B

One possible sequence:

  • ADD R3, A, B
    which directly means: R3←A+BR3 \leftarrow A + B
  • Then:
    • MOV X, R3 (store out)

What changed vs two-address?

  • The destination is separate from the sources, reducing unwanted overwrites.
  • This can make expression compilation easier (fewer temporary save/restore steps), at the cost of a longer instruction encoding (more address fields).

Worked Example: Compile $Y = (A + B) * C$ in 1-, 2-, and 3-address styles

  1. 1
    Step 1

    Let A,B,CA,B,C be input locations; YY is the output. Use ACCACC for one-address, and R1,R2,R3R1,R2,R3 for register operands in two-/three-address examples.

  2. 2
    Step 2
    1. LOAD A (ACC←A)
    2. ADD B (ACC←ACC+B)
    3. MUL C (ACC←(A+B)*C)
    4. STORE Y
  3. 3
    Step 3
    1. MOV R1, A
    2. ADD R1, B (R1←A+B)
    3. MUL R1, C (R1←(A+B)*C)
    4. MOV Y, R1
  4. 4
    Step 4
    1. ADD R1, A, B (R1←A+B)
    2. MUL R2, R1, C (R2←R1*C)
    3. MOV Y, R2

Instruction Encoding Implication (Qualitative)

Address fields typically increase from 1-address to 3-address; this often increases instruction size but can reduce temporaries/register overwrite needs.

Side-by-side comparison

FeatureOne-addressTwo-addressThree-address
Explicit operand addresses in arithmetic123
Typical implicit behavioraccumulator implicit operandone operand often overwrittendestination separate
Overwrite riskhigh (single implicit destination)medium (destination reused as source)low
Ease for expression evaluationmoderate (needs loads/stores into ACC)good (but careful about overwrites)often best for compilers

Pro Tip: Overwrite is the hidden cost

In two-address code, the instruction often overwrites a source. When translating expressions, track where values are reused so you don’t destroy a value you still need. This is one reason three-address IRs are popular in compiler middle-ends.

Warning: “Address count” can mean different things across sources

Some textbooks discuss one-/two-/three-address intermediate code formats, others discuss an ISA-level convention. The common theme is operand explicitness: one-address uses an implicit accumulator; three-address keeps destination separate.

Common questions and edge cases

Where these formats appear in a typical compiler pipeline

Parse & build IR

Front-end

Produce an intermediate representation (often conceptually closer to three-address SSA/data-flow)."

Optimizations

Middle-end

Simplify expressions; reduce temporaries; constant folding and common subexpression elimination."

Lowering to target ISA

Back-end

Translate to the target’s instruction style (one/two/three-address conventions), including register allocation."

Quick check: one-, two-, three-address

1 / 5
Question · Term

One-address arithmetic typically uses what implicit operand?

Click to reveal
Answer · Definition

An accumulator (or other implicit register) supplies one operand and often receives the result.

Knowledge Check

Question 1 of 4
Q1Single choice

In the classic definition of a one-address instruction, the second operand is typically provided by which mechanism?