Zero Address Instruction Format (Stack-Based Instruction Formats)

A zero-address instruction format is an instruction representation used in stack-based architectures: the operands are implicitly taken from the top(s) of a stack, and results are pushed back to the stack. As a result, instructions typically contain no register/memory address fields for operands—the “addressing” is handled by the stack discipline rather than by explicit operand specifiers.2

In contrast, one-, two-, and three-address formats encode explicit operand locations (registers or memory addresses) directly in the instruction. Zero-address formats are therefore closely associated with register stack organizations and virtual machine–style stacks.

Core idea

In a zero-address ISA, an arithmetic instruction like ADD does not name where operands live. Instead, the execution unit assumes that:

• the first operand is at the top of the stack (or a defined position),
• the second operand is next on the stack,
• the instruction replaces them with the result on the stack.

So the instruction format can be thought of as just an operation code plus (optionally) immediate constants or other non-address fields (e.g., PUSH c includes a literal constant, but still has no operand address).2

Key terms (learn these):

• instruction format
• stack pointer
• opcode
• operand stack

Instruction format structure

Because zero-address instructions do not explicitly name operand locations, the instruction encoding often looks like:

• Opcode-only instructions: e.g., ADD, SUB, MUL, DIV
• Opcode + immediate instructions: e.g., PUSH 5 (still no operand address; the constant is immediate)

This is why many explanations of “zero-address” emphasize that the stack location is implicit, not encoded in the instruction’s address fields.2

Benefits and trade-offs

Benefits

1. Shorter instruction encodings: with no explicit operand address fields, instruction size can be reduced.2
2. Simpler instruction format/decoding: execution can rely on the stack discipline instead of register/memory specifiers.

Trade-offs

1. More stack traffic: each operation may require pops/pushes, increasing implicit memory/register-stack activity.2
2. Harder optimization for the compiler (depending on the target): extracting parallelism or keeping values in registers can be less direct than in register-based multi-address ISAs.2

[Callout]{type="tip" title="Pro Tip"} When analyzing a zero-address instruction sequence, always track the stack effect: how many items each instruction pops and pushes. This “stack accounting” makes program reasoning much faster. [/Callout]

[Callout]{type="warning" title="Common pitfall"} Don’t confuse zero-address with zero operands. ADD still consumes operands—it just gets them implicitly from the stack rather than from explicit address fields. [/Callout]

Small worked example (stack effect)

Consider computing $(a + b) \times c$ in a stack model:

• PUSH a → stack: [a]
• PUSH b → stack: [a, b]
• ADD → pops b and a, pushes a+b → stack: [a+b]
• PUSH c → stack: [a+b, c]
• MUL → pops c and a+b, pushes (a+b)*c → stack: [(a+b)*c]

This illustrates that the “operand addresses” are implicit in stack position, not encoded in the instructions.2