Addressing Modes in Computer Architecture: Purpose, Why They Exist, and Two Modes Without Address Fields

An addressing mode describes how the CPU interprets an instruction’s operand information—i.e., whether the operand is in a register, is a literal constant, is at a computed memory address, etc. The key idea is that the same instruction format (e.g., an opcode plus some operand bits) can support multiple ways to locate operands by using an addressing mode interpretation mechanism (often encoded via an “addressing mode field” in the instruction, or implied by instruction type).

Computers use addressing modes because they improve:

• Code flexibility: instructions can refer to operands stored in different places (registers, memory, constants, stacks) without changing the entire instruction set design.
• Code density and efficiency: many common operations can use compact encodings (e.g., immediate or register-based forms) rather than forcing memory accesses.
• Performance and memory locality: selecting register/immediate modes can reduce memory traffic and latency.
• Support for different programming constructs: arrays, pointers, procedure calls, and control-flow targets naturally map to indirect/base/relative addressing forms.

Below, we formalize two addressing modes that do not use an address field (because they don’t need to name a memory address).

Note: Exact instruction-encoding details vary across ISAs (x86, ARM, RISC-V, etc.), but the conceptual model of addressing modes is consistent: it’s a contract between instruction encoding and operand location/value selection.

Core terms (quick reference)

• operand
• effective address
• immediate operand
• register operand

Why “addressing mode” exists

In a typical architecture, the CPU must decide one of several operand retrieval strategies for each instruction execution:

1. Use a literal directly (immediate)
2. Use a register value directly (register)
3. Compute a memory address (direct/indirect/base-relative/indexed/PC-relative) and then read/write memory

This is why addressing modes are “techniques”: they let the ISA define multiple operand-location rules without forcing every instruction to always carry a full memory address.

Two addressing modes without address fields

Mode 1: Immediate addressing (immediate mode)

Meaning: The operand value is contained directly in the instruction as a literal constant. No memory location needs to be specified, so there is no “address field” pointing to memory.

• immediate
• immediate addressing

Example (conceptual assembly):

• Instruction: ADD R1, #5
• Interpretation:
  • #5 is an immediate literal
  • The CPU adds the literal 5 to R1 (register value), producing the result in the destination register.

Why it needs no address field: the operand is already the constant 5—there is no memory dereference, so there is no effective address computation.

Mode 2: Register addressing (register mode)

Meaning: The operand is taken from a CPU register specified by the instruction. Again, no memory address is required.

• register addressing
• register operand

Example (conceptual assembly):

• Instruction: MOV R2, R3
• Interpretation:
  • The source operand is the value currently stored in register R3
  • The destination R2 receives that value

Why it needs no address field: registers are not addressed like memory locations in a dereference step for this mode; the instruction directly names the register (typically using register specifier bits).