Instruction Fetch Phase: What Concludes with Decoding into IR?
In the instruction cycle, the fetch stage retrieves the next instruction from memory using the Program Counter (PC) and then moves that fetched instruction into the CPU’s Instruction Register (IR). By the end of the fetch stage, the instruction is in the register that will be used for decoding in the next stage. This matches option (iv): decoding the data in MDR and placing it in IR—more precisely, the fetched instruction is transferred from MDR to IR so it can be decoded by the control unit. The fetch stage includes: (1) copy PC to MAR, (2) read memory at MAR, (3) load the fetched word into MDR, then (4) copy it into IR; the PC is also incremented as part of the fetch stage.2
Keyword anchors
- instruction cycle
- fetch stage
- MAR
- MDR
- IR
Footnotes
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Primary Instruction Cycles - GeeksforGeeks - Lists fetch-cycle steps: PC→MAR, memory read to MDR, MDR→IR, then PC increment. ↩
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Instruction cycle - Wikipedia - Describes fetch stage steps: PC→MAR, memory read to MDR, MDR→current instruction register (IR/CIR), and PC increment. ↩
Fetch–Decode–Execute Cycle (visual walkthrough)
Evaluating the Given Choices (i)–(iv)
Core idea of the fetch stage
A standard register-transfer view of the fetch stage is: PC → MAR → Memory → MDR → IR, with PC incremented during/at the end of fetch.2 This means the “end” of fetch is not executing the instruction nor loading operand data—those belong to decode/execute—rather, it is making the instruction available for decoding by moving it into IR.2
Therefore, among your options, the only one that corresponds to fetch completing with the instruction placed where decoding will occur is (iv).
Footnotes
-
Primary Instruction Cycles - GeeksforGeeks - Lists fetch-cycle steps: PC→MAR, memory read to MDR, MDR→IR, then PC increment. ↩ ↩2
-
Instruction cycle - Wikipedia - Describes fetch stage steps: PC→MAR, memory read to MDR, MDR→current instruction register (IR/CIR), and PC increment. ↩ ↩2
Typical micro-operations in the instruction fetch stage
- 1Step 1
The address of the next instruction (in the PC) is transferred into the MAR so the memory knows what location to read.
- 2Step 2
The control unit issues a memory-read signal; memory places the requested word onto the data path.
- 3Step 3
The fetched instruction word is loaded into the MDR as temporary storage.
- 4Step 4
The instruction is moved from MDR into IR so the control unit can decode it next.
- 5Step 5
The PC is updated to point to the following instruction (often as part of the fetch sequence).
Why each option is (in)correct
| Option | Claim | Status | Reason (instruction fetch vs later phases) |
|---|---|---|---|
| (i) | placing data from MAR into MDR | Partially | This transfer happens during fetch, but fetch completion is about the instruction being ready for decoding—i.e., it is moved into IR, not just into MDR. MAR is an address register; fetched data/instruction goes into MDR. |
| (ii) | placing the address of the data into MAR | Partially | This also occurs early in fetch (PC address → MAR), but “end of fetch” is not just setting the MAR; it must also deliver the fetched instruction into IR. |
| (iii) | completing execution and placing its storage address into MAR | Incorrect | “Completing execution” is the execute stage, not fetch. The fetch stage does not perform the instruction or compute where its result will be stored. |
| (iv) | decoding the data in MDR and placing it in IR | Correct in intent (but phrasing) | Fetch ends with the fetched instruction in IR (after MDR holds it). Decoding logically happens in the decode stage, but the transition MDR → IR is the defining “end of fetch.”2 |
Key point: In many textbook descriptions, “decoding” is discussed as the next phase; nonetheless, the fetch stage’s last data movement is MDR → IR, enabling decoding immediately after fetch ends.2
Footnotes
-
Primary Instruction Cycles - GeeksforGeeks - Lists fetch-cycle steps: PC→MAR, memory read to MDR, MDR→IR, then PC increment. ↩ ↩2
-
Instruction cycle - Wikipedia - Describes fetch stage steps: PC→MAR, memory read to MDR, MDR→current instruction register (IR/CIR), and PC increment. ↩ ↩2
Pro Tip: Use the “PC → MAR → MDR → IR” mnemonic
If you see PC, MAR, MDR, and IR in a question about fetch, the terminal register for the fetched instruction is IR—so look for the option that ends with MDR-to-IR (not execution, not result-addressing).
Watch the wording: decode happens after fetch
Some options say “decoding” during fetch, but most architectures place fetched instruction into IR at the end of fetch; the control unit decodes the opcode during the subsequent decode stage. The safest discriminant is: what register contains the instruction at the end of fetch—IR.2
Footnotes
-
Primary Instruction Cycles - GeeksforGeeks - Lists fetch-cycle steps: PC→MAR, memory read to MDR, MDR→IR, then PC increment. ↩
-
Instruction cycle - Wikipedia - Describes fetch stage steps: PC→MAR, memory read to MDR, MDR→current instruction register (IR/CIR), and PC increment. ↩
| Time in fetch | What moves where |
|---|---|
| Step 1 | |
| Step 2 | Memory read at |
| Step 3 | Fetched word |
| Step 4 |
Instruction cycle phases (where fetch ends)
Instruction in IR
Fetch stage endsMDR → IR completes fetch so the instruction can be decoded."
Control interprets IR
Decode stageControl unit interprets opcode/operand fields in IR."
Actual operation happens
Execute stageALU/memory/register actions according to the decoded instruction."
Common exam confusion
Knowledge Check
In a standard instruction cycle, which register holds the fetched instruction at the end of the fetch stage?