Describe the Phases in an Instruction Cycle
An instruction cycle is the core loop a CPU follows to run programs. In the most common (simplified) model, each instruction passes through phases such as instruction fetch, instruction decode, and execution. Many architectures also include a memory access and a write-back stage—especially in pipelined designs.
A useful way to remember the cycle is: get the instruction → understand it → do the work → complete any memory/register updates.
Key terms you’ll see across CPU textbooks:
- Program Counter (PC)
- Instruction Register (IR)
- ALU
- Control Unit
Instruction Cycle (Fetch–Decode–Execute) Overview
Instruction cycle phases (canonical view)
Most introductory courses describe the cycle in these phases:
- Fetch: use the PC to read the next instruction from memory into IR.
- Decode: interpret the instruction’s fields (opcode, register specifiers, immediate values, addressing mode) and generate control signals.
- Execute: perform the main operation—ALU computation, condition evaluation, or effective address calculation.
- Memory access (optional depending on instruction type): for loads/stores, read or write data memory.
- Write-back: store the final result into a register (or otherwise complete state updates).
- PC update: determine the next PC value (typically PC + instruction length, or a branch/jump target).
A single instruction can differ slightly depending on whether it’s an ALU operation, a load/store, or a control-flow instruction (branch/jump).
Phases of the Instruction Cycle (Per Instruction)
- 1Step 1
Copy the next instruction from memory into the Instruction Register (IR) using the address in the Program Counter (PC).
- 2Step 2
Parse IR to identify the opcode and operands; generate control signals for the rest of the cycle.
- 3Step 3
Run the core operation in the ALU or compute an effective address for memory operations.
- 4Step 4
If it’s a load, read from data memory; if it’s a store, write to data memory.
- 5Step 5
Place the computed result (or loaded data) into the destination register; complete any required architectural updates.
- 6Step 6
Advance PC (e.g., PC + fixed instruction length) or set PC to a branch/jump target based on control-flow evaluation.
How to classify instructions by phases
If an instruction uses the ALU only (e.g., add/sub/compare), it typically completes in Fetch→Decode→Execute→(Write-back) with no Memory Access. If it loads/stores, it includes Memory Access. If it branches/jumps, PC update depends on the executed condition/target.
Why pipelining changes the “shape” of phases
In pipelined CPUs, multiple instructions overlap in time. So you still have the same conceptual phases, but different instructions occupy different stages simultaneously—making timing and hazards (stalls/forwarding) important.
Extended phase model for pipelined / Harvard-style discussions
In a more detailed, pipeline-oriented model (common in RISC teaching), phases often map to stages like:
- IF (Instruction Fetch): PC → instruction memory → IR
- ID (Instruction Decode/Register Fetch): decode + read register file
- EX (Execute/Address Calculation): ALU op or branch comparison; effective address for loads/stores
- MEM (Memory Access): data memory read/write
- WB (Write Back): write result to register file
- (Often PC update is associated with branch decisions in EX and later stage timing.)
This mapping helps explain why load/store require MEM, while ALU operations can bypass it.
Phase Coverage by Common Instruction Types
Conceptual checklist of which phases are typically involved.
Overlapping Phases in a Simple 5-Stage Pipeline
IF
Cycle 1Instruction I1 is fetched."
ID (I1), IF (I2)
Cycle 2I1 decodes while I2 is fetched."
EX (I1), ID (I2), IF (I3)
Cycle 3I1 executes; I2 decodes; I3 fetches."
MEM (I1), EX (I2), ID (I3), IF (I4)
Cycle 4I1 may access memory; others progress."
WB (I1), MEM (I2), EX (I3), ...
Cycle 5I1 writes back; pipeline continues with overlap."
Common Edge Cases & Clarifications
Instruction Cycle Phases (Quick Recall)
Knowledge Check
Which phase is most responsible for interpreting the opcode and determining control signals?