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CPU Instruction Fetch: Sequence of Micro-operations During a Typical Fetch

CPU Instruction Fetch: Sequence of Micro-operations During a Typical Fetch

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Nov 3, 2026

A typical instruction fetch in the classic register-transfer model uses these CPU registers: Program Counter (PC) , Memory Address Register (MAR) , Memory Data Register (MDR) , and Instruction Register (IR).

In the standard fetch flow, the processor:

  1. uses the PC as the source of the next instruction address,
  2. loads that address into MAR,
  3. reads memory into [MDR]{def="Holds data read from memory before transfer},
  4. transfers the fetched instruction from MDR into IR.

This corresponds to option (i) PC → MAR → Memory → MDR → IR.

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Instruction Fetch (Classic Register-Transfer Sequence)

  1. 1
    Step 1

    Copy the next instruction address from the PC into the MAR.

  2. 2
    Step 2

    Memory uses the address in the MAR to perform a read.

  3. 3
    Step 3

    The fetched instruction word is placed into the MDR.

  4. 4
    Step 4

    "Transfer the instruction from MDR into the IR."

    Footnotes

    1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Why MAR and MDR usually appear

In many CPU datapaths, MAR isolates where to read from (address), and MDR isolates what you read (data) before it is committed into IR. That’s why the fetch sequence typically includes both registers.

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Beware of oversimplified variants

Some simplified textbooks omit MAR/MDR and jump straight from PC to IR. But in the classic fetch cycle with explicit registers, MAR and MDR are distinct pipeline stages for address and data movement.

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Answer Selection: Compare Fetch Sequences

Only sequence (i) matches the classic PC→MAR address phase and Memory→MDR→IR data phase.

Fetch Timeline (Chronological View)

Address sourced

t1

PC provides the next instruction address to MAR. "

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Memory read

t2

Memory reads using the address in MAR. "

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Data captured

t3

Instruction word is captured in MDR. "

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

Instruction latched

t4

Instruction is transferred from MDR into IR. "

Footnotes

  1. "Instruction Fetch Cycle (PC, MAR, MDR, IR) - CPU micro-operations" (Register-transfer description) https://www.cs.umd.edu/class/spring2017/cmsc411/ (Course notes/lecture materials explaining fetch micro-operations with PC→MAR→Memory→MDR→IR; used for mapping standard register-transfer steps.) ↩

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In the classic register-transfer model, what is the typical sequence of events during a fetch operation?

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