Control Unit of the Basic Computer: Block Diagram and Control Timing Diagrams

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Nov 4, 2026

A basic computer (in the Mano-style “basic computer” model) uses a Control Unit to coordinate register transfers across timing states such as instruction fetch, decode, and execution. The control unit’s internal organization is typically described as: an Instruction Register feeding a Decoder plus a Timing and Control Logic that produces control signals for the datapath.

A standard way to communicate how the control unit behaves is via control timing diagrams where each T-state (e.g., $T_0, T_1, T_2, \ldots$ ) is mapped to the control signals asserted during instruction fetch, memory reference, register reference, and branch-type operations.

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Basic Computer (Mano) — Control Unit & Timing (instruction fetch/execute)

Draw the Control Unit block diagram (basic computer model)

1
Step 1
Identify inputs: opcode from the Instruction Register, status/condition flags from the I/O & status logic (e.g., carry/zero where applicable), and a Clock.
2
Step 2
Add a T-state counter / Timing generator that advances through fetch/decode/execute cycles and provides the current timing state to the control logic.
3
Step 3
Add a combinational Decoder that maps (opcode + timing state) to a set of control signals for the datapath.
4
Step 4
If modeling synchronous control, include control latches so that control lines change only on intended edges.
5
Step 5
Draw outputs to: (a) Program Counter, (b) instruction memory interface, (c) Register File / Accumulator path, (d) ALU control, and (e) memory read/write and bus gating lines.

Block Diagram (what to draw)

Use this as a drawing checklist:

Key blocks to label explicitly:

Instruction Register (input to decoder)
Timing Generator (drives micro-timing)
Decoder (opcode + timing → signals)
control outputs to PC, memory, register paths, ALU

Control timing diagrams: how to read them

A control timing diagram is drawn as:

Horizontal axis: time states $T_0, T_1, T_2, \ldots$
Vertical axis: control signals such as $PC \leftarrow PC+1$ , $IR \leftarrow M[PC]$ , $MAR \leftarrow IR\_\text{addr}$ , $AC \leftarrow AC \pm M[addr]$ , etc.
A control signal is asserted during those $T$ -states where the operation must occur.

Pro Tip: In timing diagrams, keep combinational decode assumptions consistent: if the model assumes “control outputs are valid during a specific $T_k$ window,” only assert them in that $T_k$ .

Typical fetch → decode → execute lifecycle (T-states)

Fetch start

Select PC to memory address path; begin memory read of instruction."

Fetch complete / IR load

Load fetched instruction into Instruction Register; increment or prepare PC update."

Decode

Decoder uses opcode + timing state to select the required micro-operations."

Execute (varies by instruction class)

T3…

Memory reference / register reference / branch-type operations proceed with dedicated T-states."

Return to fetch

Final T-state

Control transitions back so the next instruction fetch begins."

Example timing signals to include in your diagram

Even if your exact T-state numbering varies by textbook, ensure your diagram includes these categories of control signals:

Instruction fetch controls
- $MAR \leftarrow PC$ (if MAR exists)
- $IR \leftarrow M[MAR]$
- $PC \leftarrow PC+1$ (or equivalent next-PC update)
Effective address / operand fetch controls (for memory-reference instructions)
- $AR \leftarrow IR\_\text{address}$ (or EA computation)
- $M\_data \leftarrow M[EA]$ (memory read)
ALU / register update controls
- $AC \leftarrow AC \ \text{op}\ M[EA]$
- Update carry/extend flags where applicable
Write-back controls
- $M[EA] \leftarrow AC$ for store-type instructions
- $PC \leftarrow EA$ for branch/jump when conditions satisfied
Register-reference controls
- Controls for shifts/clears/complements that operate directly on Accumulator and flags

How to draw a clean timing diagram

Start with fetch (same for all instructions), then add conditional branches: draw waveforms where the branch control lines are asserted only in the T-states when the condition is checked.

Mermaid-style timing sketch (template)

Below is a template timing diagram (replace control names and exact $T$ -state boundaries with the ones used in your specific “basic computer” reference):

What you should do in your final drawing:

Replace the generic signals with the exact signals from your course/text (e.g., $PC\_out$ , $PC\_in$ , $IR\_in$ , $Read$ , $Write$ , $ALU\_op$ ).
Ensure the ordering matches the data dependencies (e.g., you can’t update $AC$ before the operand $M[EA]$ is read).

Common pitfalls when explaining control timing

Knowledge Check

Question 1 of 4

Q1Single choice

In a basic computer timing diagram, which component primarily determines which control signals are asserted for a given instruction during T-states?

The decoder that maps opcode + timing state to control signals

The ALU only, independent of opcode

The memory only, without considering T-states

The clock frequency alone, without control logic

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