Designing a Simple Hypothetical CPU: Instruction Set, Datapath, and Control
Pro Tip: Start with a single instruction walkthrough
Pick one instruction (e.g., LW) and trace: PC → IR → decode → ALU EA → memory read → register writeback. Then replicate the pattern for other instruction classes.
Beware of PC update timing
"In branch instructions, PC can be updated conditionally; multi-cycle designs typically separate “compute branch target/condition” from “write PC” via dedicated control signals or states. Get the cycle/stage boundaries consistent with your datapath.2"
Comparison Chart: Single-Cycle vs Multi-Cycle Control
Footnotes
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multi-cycle-datapath.pdf - Discusses “Defining the Control,” how control signals are asserted per state/step, and conditional PC updates. ↩
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CS274: Computer Architecture - The MIPS Multi Cycle Design | CS274 - Explains multicycle execution steps and control sequencing via an FSM over instruction stages. ↩
Control Complexity Drivers (qualitative)
Relative conceptual complexity; does not measure cycle time.
Processor Design: Datapath, Decode, Execute, Memory Access, Register Writeback (RISC-V)
FAQ on Simple CPU Design
Knowledge Check
In a multi-cycle CPU, which component most naturally defines the sequence of operations across clock cycles?