Integrated Diagram: TLB and Cache Operations for a Logical/Virtual Address

A modern processor typically performs address translation (virtual $\rightarrow$ physical) via a keywordTLB/keyword, and then performs a cache lookup (using the resulting address) in one or more **keywordcaches/keyword.

The most integrated “mental model” is: TLB lookup gates the cache lookup, because many cache designs are indexed/tagged with the physical address after translation.

Below is a unified diagram for a single logical/virtual address generated by the processor, showing both the TLB path and cache path, including the main miss/retry flows. (The exact internal policy—e.g., whether the cache lookup is partially speculative—is implementation dependent.)

Key points captured by the diagram:

• keywordTLB hit/keyword: Translation exists; cache lookup can proceed using PA.
• keywordTLB miss/keyword: A **keywordpage-table walk/keyword runs (often involving additional memory reads), then the TLB is updated and the request is retried.
• Cache miss flow: After PA is known, lookup continues through lower cache levels and/or memory until the block/line is fetched and filled.

To further ground the diagram, here’s a compact “decision table” aligning the two subsystems:

keywordPA/keyword becomes the common “currency” for caching in many designs, while keywordVA/keyword is what the TLB consumes.