Timing diagrams are graphical representations of how digital signals change with time; in the 8051 context, they show the relative transitions of clock-derived control lines such as ALE, PSEN, RD, WR, and the multiplexed address/data buses during instruction fetch and data access 2. Understanding these diagrams is essential because the classic 8051 is a 12-clock architecture: one machine cycle consists of 12 oscillator periods, organized as 6 states, with each state spanning 2 oscillator periods 2. Instruction execution is then measured in machine cycles, so performance analysis reduces to counting cycles and converting them into time using

$$T_{\text{inst}} = \frac{12 \times C}{f_{\text{osc}}}$$

for an instruction requiring $C$ machine cycles on a standard 12-clock 8051 2.

A key practical consequence is that many ordinary instructions complete in 1 machine cycle, some branch and loop-related instructions require 2 machine cycles, and operations such as MUL AB and DIV AB take 4 machine cycles on the classic core 2. During external program memory fetches, Port 0 carries the low-order address first and later the code byte, Port 2 carries the high-order address, ALE latches the low address externally, and PSEN provides the active-low read strobe to program memory 2. During internal program execution, PSEN is not used for internal code fetches and remains inactive/high, while ALE still continues at its clock-derived rate except in cases such as certain external data accesses where pulses may be skipped 2.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵

2. Intel MCS-51 User's Manual mirror - Additional accessible copy of Intel documentation covering external program-memory fetch and bus multiplexing. ↩ ↩²

3. Embedded Systems/8051 Microcontroller - Wikibooks - Overview of oscillator, states, and the 12-clock machine-cycle model. ↩

4. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩ ↩²

5. Overview of the 8051 Microcontroller - Educational summary listing examples of 1-cycle, 2-cycle, and 4-cycle instructions. ↩

6. P87C554 - 80C51 8-bit microcontroller – 12 clock operation - Vendor datasheet noting ALE activation every six oscillator periods and skipped ALE pulses during external data memory access. ↩

1. What a timing diagram represents

A timing diagram places multiple digital signals on aligned horizontal tracks, with time increasing from left to right, so that the designer can see when a signal becomes valid, how long it remains active, and which signal transitions trigger another event 2. In the 8051, these diagrams are especially important because external memory operations use time-multiplexed buses: the same physical Port 0 pins carry address information during one portion of the cycle and data during another 2.

For 8051 analysis, the most common signals are:

The distinction between program memory timing and external data memory timing is fundamental. PSEN belongs to code fetches, whereas RD and WR belong to external data accesses, and the CPU schedules them differently because a data memory bus cycle occupies more bus time than a normal program fetch .

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸ ↩⁹

2. Intel MCS-51 User's Manual mirror - Additional accessible copy of Intel documentation covering external program-memory fetch and bus multiplexing. ↩ ↩² ↩³ ↩⁴ ↩⁵

3. P87C554 - 80C51 8-bit microcontroller – 12 clock operation - Vendor datasheet noting ALE activation every six oscillator periods and skipped ALE pulses during external data memory access. ↩

2. Machine cycle concept in the 8051

The classic Intel MCS-51 timing model defines a machine cycle as the basic internal execution interval of the CPU . It consists of:

• 6 states: $S1$ through $S6$ 2
• 2 oscillator periods per state 2
• therefore 12 oscillator periods per machine cycle 2

If the oscillator frequency is $f_{\text{osc}}$, then machine-cycle duration is

$$T_{\text{MC}} = \frac{12}{f_{\text{osc}}}$$

For the common crystal frequency of 11.0592 MHz, this becomes approximately

$$T_{\text{MC}} \approx \frac{12}{11.0592 \times 10^6} \approx 1.085 \ \mu s$$

on a standard 12-clock 8051 2.

This timing base also drives peripheral behavior. Timers on the original 8051 increment at the machine-cycle rate in timer mode, which is why instruction timing, peripheral timing, and waveform generation are tightly linked in system analysis 2.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵

2. Embedded Systems/8051 Microcontroller - Wikibooks - Overview of oscillator, states, and the 12-clock machine-cycle model. ↩ ↩² ↩³ ↩⁴ ↩⁵

3. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩

3. Instruction execution patterns: 1-cycle, 2-cycle, and multi-cycle

The 8051 instruction set is documented in terms of bytes and machine cycles, and cycle count is independent of whether program memory is internal or external 2. Typical categories are:

• 1-cycle instructions: many arithmetic, data transfer, and bit operations such as ADD, MOV, SETB, NOP, DEC, INC 2
• 2-cycle instructions: common conditional jumps, decrement-and-jump patterns, and MOVX external data memory operations 3
• 4-cycle instructions: MUL AB and DIV AB 2

A subtle but important point is that the 8051 overlaps instruction fetching with current instruction execution. According to the Intel user manual, execution of a one-cycle instruction begins when the opcode is latched into the instruction register in State 1, and another fetch occurs later in the same machine cycle . That overlapping fetch behavior is why timing diagrams often show more bus activity than a simplistic “fetch, then execute, then fetch again” picture would suggest.

A representative classification is shown below.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴

2. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸

3. Overview of the 8051 Microcontroller - Educational summary listing examples of 1-cycle, 2-cycle, and 4-cycle instructions. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶

4. Fetch-decode-execute cycle in timing terms

Conceptually, instruction execution follows a fetch-decode-execute pattern, but on the 8051 this is partially overlapped across states and machine cycles . The CPU:

1. Fetches the opcode from program memory
2. Latches it into the instruction register and decodes it
3. Fetches additional bytes if the instruction length requires them 2
4. Performs the operation, which may include ALU work, internal memory access, or external memory access 2
5. Fetches the next opcode, often before the current instruction has fully completed

This overlapping is central to interpreting timing diagrams. For instance, even while a one-cycle instruction is executing, another program fetch can be visible on the external bus when code memory is external . By contrast, during the second machine cycle of a MOVX instruction, normal program fetches are skipped because the external bus is committed to the data memory access .

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸

2. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩ ↩²

5. External program memory timing: ALE, PSEN, and multiplexed buses

When the 8051 executes code from external program memory, it uses a multiplexed bus arrangement 2:

• Port 0 carries A0–A7 first, then becomes the data bus for the fetched opcode byte 2
• Port 2 carries A8–A15 throughout the access 2
• ALE strobes an external latch so that the low address remains stable after Port 0 changes function 2
• PSEN goes active low to read code bytes from external program memory 2

The Intel manual states that when program memory is external, PSEN is normally activated twice per machine cycle . This aligns with the fact that there are two code fetch opportunities within the machine-cycle timing structure. Secondary sources also note that ALE is activated every six oscillator periods and commonly appears twice per machine cycle under normal operation .

A compact conceptual timing view is:

Two ideas matter here:

1. ALE defines address capture timing 2
2. PSEN defines external code-read timing 2

If execution instead comes from internal program ROM, then those external PSEN fetch strobes are not needed for the code fetch path, so PSEN remains inactive/high during internal program execution 2.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸ ↩⁹

2. Intel MCS-51 User's Manual mirror - Additional accessible copy of Intel documentation covering external program-memory fetch and bus multiplexing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶

3. P87C554 - 80C51 8-bit microcontroller – 12 clock operation - Vendor datasheet noting ALE activation every six oscillator periods and skipped ALE pulses during external data memory access. ↩ ↩² ↩³

6. Why PSEN is active every six oscillator periods

Because one machine cycle contains 12 oscillator periods, a signal that appears twice per machine cycle naturally repeats every 6 oscillator periods 2. Vendor datasheets for 12-clock 8051-compatible devices explicitly describe ALE as being activated every six oscillator periods, and the Intel manual describes PSEN as normally being activated twice per machine cycle during external code execution 2.

Therefore, the statement often taught in 8051 timing analysis is:

• During external program execution: PSEN is seen as periodic low pulses associated with code fetches, effectively tied to the half-machine-cycle fetch rhythm
• During internal program execution: PSEN stays inactive/high because no external code fetch is needed 2

This distinction is central when diagnosing hardware with an oscilloscope. A continuously pulsing PSEN usually indicates external code fetch activity, whereas a high/inactive PSEN suggests internal code execution or no external program read in progress 2.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵

2. P87C554 - 80C51 8-bit microcontroller – 12 clock operation - Vendor datasheet noting ALE activation every six oscillator periods and skipped ALE pulses during external data memory access. ↩ ↩²

3. Intel MCS-51 User's Manual mirror - Additional accessible copy of Intel documentation covering external program-memory fetch and bus multiplexing. ↩ ↩²

7. External data memory access timing: RD and WR during MOVX

External data memory belongs to a separate address space from program memory in the 8051 architecture . Accesses to it are performed by MOVX instructions, and the CPU generates:

• RD for external data memory reads
• WR for external data memory writes

The Intel manual emphasizes two important timing facts :

1. MOVX instructions take 2 machine cycles
2. No program fetch is generated during the second cycle of a MOVX instruction; this is the only time program fetches are skipped

This explains why external data memory timing diagrams look different from ordinary instruction fetch timing diagrams. The external bus is occupied by the data access, so the expected PSEN fetch strobes are absent during that interval . The same source also notes that a data memory bus cycle takes twice as much time as a program memory bus cycle .

For MOVX @DPTR variants, the full 16-bit address is typically formed using DPTR and emitted across Port 0 and Port 2; for MOVX @Ri, an 8-bit indirect addressing form is used as documented in instruction references 2.

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷

2. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩

8. Comparing program-memory and data-memory timing

The following comparison helps distinguish the bus behavior:

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸ ↩⁹ ↩¹⁰ ↩¹¹ ↩¹² ↩¹³

2. Intel MCS-51 User's Manual mirror - Additional accessible copy of Intel documentation covering external program-memory fetch and bus multiplexing. ↩ ↩² ↩³

3. P87C554 - 80C51 8-bit microcontroller – 12 clock operation - Vendor datasheet noting ALE activation every six oscillator periods and skipped ALE pulses during external data memory access. ↩

9. Applying timing analysis to performance calculations

Instruction timing analysis is indispensable for estimating real execution speed. On the classic 8051, if a sequence contains instruction cycle counts $C_1, C_2, \dots, C_n$, then total execution time is

$$T_{\text{total}} = \frac{12}{f_{\text{osc}}}\sum_{i=1}^{n} C_i$$

2

For example, suppose a code fragment contains:

• MOV A,R1 = 1 cycle
• ADD A,#data = 1 cycle
• DJNZ R2,LOOP = 2 cycles

Then one pass through the three instructions costs:

$$1 + 1 + 2 = 4 \text{ machine cycles}$$

At 12 MHz:

$$T = 4 \times 1\mu s = 4\mu s$$

approximately 2.

For an external RAM transfer like MOVX A,@DPTR, the instruction takes 2 machine cycles 2, so at 11.0592 MHz:

$$T \approx 2 \times 1.085\mu s = 2.17\mu s$$

This kind of calculation is the basis for:

• delay-loop design 2
• bus throughput estimation
• real-time response analysis 2
• timer preload calculations

Footnotes

1. MCS-51 Microcontroller Family User's Manual - Primary Intel reference describing machine cycles, fetch/execute timing, PSEN, ALE, MOVX, and external bus timing. ↩ ↩² ↩³ ↩⁴

2. Atmel 8051 Microcontrollers Hardware Manual - Instruction set reference with cycle counts for classic 8051-compatible instructions. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶

3. Embedded Systems/8051 Microcontroller - Wikibooks - Overview of oscillator, states, and the 12-clock machine-cycle model. ↩ ↩² ↩³ ↩⁴

4. Overview of the 8051 Microcontroller - Educational summary listing examples of 1-cycle, 2-cycle, and 4-cycle instructions. ↩