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Microprocessor

Memory Structures - Data and Program Memory

1.5 hours

Learning Goals

  • Understand the complete memory organization of the 8051 with separate data and program memory spaces (Harvard architecture)
  • Describe the data memory (internal RAM) organization: register banks (00H-1FH), general-purpose RAM (20H-7FH), and SFR space (80H-FFH)
  • Explain the concept of memory banks and how they are selected through register bits in PSW
  • Identify the bit-addressable area in RAM: specifically the 16 bytes from 20H to 2FH that support bit-level operations
  • Analyze the structure and function of each register bank (4 banks × 8 registers)
  • Understand program memory (ROM) capacity in standard 8051 (4KB) and how it's addressed by the 16-bit PC
  • Distinguish between byte addressing (for data memory) and bit addressing (for specific RAM locations)
  • Explain how bit addressing is implemented in the instruction set for bitwise operations on bit-addressable locations

In the 8051 microcontroller, memory organization is fundamental to understanding how instructions execute and how data is stored. The 8051 uses a Harvard architecture, meaning program memory and data memory are treated as separate logical spaces rather than one shared memory map.2 This separation allows the CPU to fetch instructions from code memory while independently operating on data memory, which is one reason the 8051 became highly effective for embedded control applications.2

For the standard 8051, the key memory facts are:

  • Program memory (code memory): 4 KB on-chip ROM, occupying addresses 0000H–0FFFH when internal code memory is enabled.2
  • Program Counter (PC): 16-bit, so the CPU can address up to 64 KB of code space in total.2
  • Internal data memory (RAM): 128 bytes, mapped from 00H–7FH in the original 8051.2
  • The internal RAM is divided into:
    • Register banks: 00H–1FH
    • Bit-addressable RAM: 20H–2FH
    • General-purpose RAM: 30H–7FH2
  • Special Function Registers (SFRs): 80H–FFH, used to control CPU, ports, timers, serial interface, interrupts, and status flags.2

A useful way to think about the 8051 is that it has two major memory worlds:

This topic is especially important in 8051 programming because many instructions depend directly on whether an operand is in register space, direct RAM, bit-addressable RAM, or SFR space.2

Footnotes

  1. MICROCONTROLLERS LEARNING OBJECTIVES - Describes Harvard architecture and identifies the 8051 as using separate program and data memories. ↩

  2. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩ ↩2 ↩3 ↩4

  3. 8051 Memory Organization - Annamalai University - Summarizes program memory and data memory separation in the 8051. ↩

  4. Block Diagram of 8051 Microcontroller - States that internal ROM occupies code memory 0000H-0FFFH in the standard 8051. ↩

  5. 8051 Hardware Overview - Documents 16-bit PC, EA, PSEN, and the 64 KB code-space map. ↩

  6. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2 ↩3

  7. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩ ↩2 ↩3

  8. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩

  9. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

Memory organization of 8051 | Data memory organization of 8051 microcontroller

Core Idea

The 8051 does not treat program memory and data memory as one combined address map. Code bytes are fetched from program memory, while variables and registers are accessed in data memory.2

Footnotes

  1. MICROCONTROLLERS LEARNING OBJECTIVES - Describes Harvard architecture and identifies the 8051 as using separate program and data memories. ↩

  2. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩

1. Harvard Architecture in the 8051

The 8051 follows the Harvard model, where code memory and data memory are distinct spaces.2 Even if both spaces conceptually contain addresses like 0000H, those addresses belong to different memory domains. Thus:

  • 0000H in program memory refers to the start of the instruction space.
  • 00H in data memory refers to the first byte of internal RAM.

This distinction is visible in the instruction set:

  • Instructions such as MOV operate on internal data memory or SFRs.
  • Instructions such as MOVC access code memory.
  • Instructions such as MOVX access external data memory.

Because the spaces are separate, the same numeric address does not imply the same physical meaning across program and data memory.2

This architecture also explains why the 8051 has specialized instructions for different memory spaces rather than a single uniform load/store scheme.2

Footnotes

  1. MICROCONTROLLERS LEARNING OBJECTIVES - Describes Harvard architecture and identifies the 8051 as using separate program and data memories. ↩

  2. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩ ↩2 ↩3

  3. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

  4. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩ ↩2 ↩3

  5. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Lists Boolean manipulation, stack behavior, and memory-access instructions such as MOV, MOVX, and bit instructions. ↩ ↩2 ↩3

How the 8051 Data Memory Is Organized

  1. 1
    Step 1

    In the original 8051, internal data RAM occupies addresses 00H to 7FH, giving a total of 128 bytes.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  2. 2
    Step 2

    Addresses 00H to 1FH are divided into four register banks, each containing eight registers named R0 to R7.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  3. 3
    Step 3

    Addresses 20H to 2FH form a 16-byte area whose 128 individual bits can each be addressed directly by bit-oriented instructions.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  4. 4
    Step 4

    Addresses 30H to 7FH are used as ordinary byte-addressable RAM for variables, temporary storage, and often the stack.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  5. 5
    Step 5

    Addresses 80H to FFH are assigned to Special Function Registers, which control peripherals and core functions such as ACC, B, PSW, SP, DPTR, I/O ports, timers, interrupt control, and serial communication.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩

2. Internal Data Memory Map

The internal data memory structure of the standard 8051 can be summarized as follows:3

Address RangeSizePurposeAddressing Style
00H–1FH32 bytes4 register banks × 8 registersRegister/direct
20H–2FH16 bytesBit-addressable RAMByte + bit
30H–7FH80 bytesGeneral-purpose RAMByte
80H–FFH128 bytesSFR spaceDirect only for SFR access

Two important clarifications are necessary:

  1. In the original 8051, the main internal RAM universally discussed for programming is the lower 128 bytes (00H–7FH).2
  2. The SFR space (80H–FFH) is not ordinary RAM; it contains control registers for hardware functions.2

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2 ↩3

  2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩ ↩2

  3. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩ ↩2

  4. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

Common Confusion

Addresses 80H to FFH are not general-purpose RAM in the standard 8051. They represent Special Function Registers, and these are primarily accessed by direct addressing instructions.2

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

  2. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

3. Register Banks: 00H–1FH

The first 32 bytes of internal RAM are organized as four register banks, and each bank contains eight 8-bit registers named R0 through R7.2

BankAddress RangeRegisters
Bank 000H–07HR0–R7
Bank 108H–0FHR0–R7
Bank 210H–17HR0–R7
Bank 318H–1FHR0–R7

Only one bank is active at a time for instructions that refer to registers by name, such as MOV A, R3.2 Which bank is active depends on the RS1 and RS0 bits in the PSW (Program Status Word).2

The bank selection table is:

RS1RS0Active BankRAM Addresses
00Bank 000H–07H
01Bank 108H–0FH
10Bank 210H–17H
11Bank 318H–1FH

By default after reset, Bank 0 is typically selected because PSW starts cleared in the standard architecture.2

This banked structure is useful because register instructions are compact and efficient, and bank switching can reduce context-saving overhead in interrupt-driven systems.2

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2 ↩3

  2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩ ↩2 ↩3

  3. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩

  4. THE 8051 INSTRUCTION SET - Includes standard SFR reset values such as PSW and SP relevant to bank selection and stack behavior. ↩

  5. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  6. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

Understanding Register Banks and PSW Selection

4. Structure and Function of Each Register Bank

Each bank contains the same logical register names:

  • R0
  • R1
  • R2
  • R3
  • R4
  • R5
  • R6
  • R72

But their physical addresses differ by bank:

Logical RegisterBank 0Bank 1Bank 2Bank 3
R000H08H10H18H
R101H09H11H19H
R202H0AH12H1AH
R303H0BH13H1BH
R404H0CH14H1CH
R505H0DH15H1DH
R606H0EH16H1EH
R707H0FH17H1FH

A crucial programming implication is this:

  • MOV A, R2 uses the currently selected bank.
  • MOV A, 12H accesses the RAM byte at address 12H directly, which corresponds physically to R2 of Bank 2 whether or not Bank 2 is currently selected.2

This is the difference between register addressing by name and direct byte addressing by address.

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2 ↩3

  2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩ ↩2

  3. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

How Register Bank Selection Works Through PSW

  1. 1
    Step 1

    The Program Status Word is an SFR that contains status flags and the register bank select bits RS1 and RS0.

    Footnotes

    1. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩

  2. 2
    Step 2

    These two bits determine which bank becomes active for register names R0 through R7.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  3. 3
    Step 3

    The combinations 00, 01, 10, and 11 select Bank 0, Bank 1, Bank 2, and Bank 3 respectively.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  4. 4
    Step 4

    Instructions like MOV A,R5, ADD A,R2, or MOV R1,#data now operate on the selected bank only.

    Footnotes

    1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  5. 5
    Step 5

    If a programmer wants a specific physical RAM location regardless of bank selection, direct addressing such as MOV A,15H is used instead of symbolic R5.2

    Footnotes

    1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩

    2. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

1; Select register bank 2
2CLR PSW.3      ; RS0 = 0
3SETB PSW.4     ; RS1 = 1
4
5; Now R0-R7 refer to addresses 10H-17H
6MOV A, R0      ; A <- RAM[10H]
7MOV R7, #55H   ; RAM[17H] <- 55H

5. Bit-Addressable RAM: 20H–2FH

One of the most distinctive features of the 8051 is its support for bit-level processing. The 16 bytes from 20H to 2FH are special because each bit inside these bytes can be addressed individually.3

This means:

  • As bytes, the region spans 16 bytes.
  • As bits, it provides 128 directly addressable bits.2
  • Bit addresses range from 00H to 7FH.2

So the area is both:

  • byte-addressable as locations 20H to 2FH, and
  • bit-addressable as individual bit addresses 00H to 7FH.2

For example:

  • Byte address 20H contains 8 bits with bit addresses 00H to 07H.
  • Byte address 21H contains bit addresses 08H to 0FH.
  • ...
  • Byte address 2FH contains bit addresses 78H to 7FH.

A useful mapping rule is:

Bit address=8×(byte address−20H)+bit position\text{Bit address} = 8 \times (\text{byte address} - 20H) + \text{bit position}

where bit position ranges from 0 to 7.2

For instance, the bit address for bit 2 of byte 26H is:

8×(26H−20H)+2=8×6+2=50=32H8 \times (26H - 20H) + 2 = 8 \times 6 + 2 = 50 = 32H

So bit 2 of RAM byte 26H corresponds to bit address 32H.

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2 ↩3 ↩4 ↩5 ↩6 ↩7 ↩8 ↩9 ↩10

  2. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩ ↩2 ↩3 ↩4 ↩5

  3. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

6. Byte Addressing vs Bit Addressing

The 8051 supports two important ways of referring to data locations:

Byte Addressing

A full 8-bit memory location is accessed at once.

Examples:

  • MOV A, 30H
  • MOV 2AH, #55H

Here the operand refers to an entire byte.

Bit Addressing

A single bit is accessed directly.2

Examples:

  • SETB 25H
  • CLR 32H
  • JB 12H, LABEL

Here the operand refers to an individual bit in either:

  • the bit-addressable RAM area (00H–7FH as bit addresses), or
  • bit-addressable SFR bits (80H–FFH where supported).2

This distinction is crucial because bit addressing enables highly efficient Boolean control logic without read-modify-write software sequences typical of many other architectures.

Footnotes

  1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩ ↩2 ↩3 ↩4

  2. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩ ↩2 ↩3

Why Bit Addressing Matters

Bit-addressable RAM is extremely useful for flags, status indicators, control signals, and finite-state logic. Instead of masking a byte manually, the 8051 can set, clear, test, or branch on one bit directly.2

Footnotes

  1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  2. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

How Bit Addressing Is Implemented in the 8051 Instruction Set

  1. 1
    Step 1

    The target must be either one of the 128 bits in RAM bytes 20H to 2FH, or a bit-addressable SFR bit in the SFR region.2

    Footnotes

    1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

    2. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

  2. 2
    Step 2

    Bit operations in the 8051 use direct bit addresses rather than register-indirect addressing.2

    Footnotes

    1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

    2. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

  3. 3
    Step 3

    The instruction set provides dedicated bit operations such as SETB bit, CLR bit, CPL bit, MOV C,bit, MOV bit,C, ANL C,bit, ORL C,bit, and conditional branches like JB, JNB, and JBC.3

    Footnotes

    1. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Lists Boolean manipulation, stack behavior, and memory-access instructions such as MOV, MOVX, and bit instructions. ↩

    2. C51 Family - Keil - Describes lower 128-byte RAM use, direct/indirect access, and bit-oriented instruction capabilities. ↩

    3. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Provides opcode-level descriptions of SETB, CLR, CPL, JB, JNB, JBC, ANL, ORL, and MOV involving bit operands. ↩

  4. 4
    Step 4

    Because the architecture supports one-bit operands natively, individual flags can be tested or modified without loading and masking a whole byte first.2

    Footnotes

    1. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

    2. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

  5. 5
    Step 5

    Instructions such as JB and JNB directly connect bit state to branching logic, making the 8051 especially strong in control-oriented applications.2

    Footnotes

    1. C51 Family - Keil - Describes lower 128-byte RAM use, direct/indirect access, and bit-oriented instruction capabilities. ↩

    2. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Provides opcode-level descriptions of SETB, CLR, CPL, JB, JNB, JBC, ANL, ORL, and MOV involving bit operands. ↩

1SETB 20H    ; Set bit address 20H
2CLR 20H     ; Clear bit address 20H
3CPL 20H     ; Complement bit address 20H
4MOV C,20H   ; Copy bit into carry
5MOV 21H,C   ; Copy carry into bit

7. General-Purpose RAM: 30H–7FH

After the register-bank area and bit-addressable section, the remaining 80 bytes from 30H to 7FH are available as general-purpose internal RAM.2 This region is commonly used for:

  • local variables,
  • counters,
  • buffers,
  • temporary arithmetic storage,
  • stack usage depending on program design.2

Unlike the 20H–2FH region, this area is byte-addressable only; its bits are not individually addressable through the bit instruction set.2

Another important practical detail is that the stack also resides in internal RAM unless carefully managed otherwise. Since the Stack Pointer (SP) defaults to 07H after reset, the stack initially grows from 08H upward, which can overlap with register-bank space unless the programmer relocates it.2

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2

  2. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩ ↩2

  3. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Lists Boolean manipulation, stack behavior, and memory-access instructions such as MOV, MOVX, and bit instructions. ↩ ↩2

  4. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  5. C51 Family - Keil - Describes lower 128-byte RAM use, direct/indirect access, and bit-oriented instruction capabilities. ↩

Stack Placement Caution

Because the stack grows upward in internal RAM and the default SP value is 07H, careless stack use may interfere with register banks or low RAM locations. Many programs move the stack into higher RAM such as the 30H-7FH region.2

Footnotes

  1. Section 1 8051 Microcontroller Instruction Set - Microchip Technology - Lists Boolean manipulation, stack behavior, and memory-access instructions such as MOV, MOVX, and bit instructions. ↩

  2. C51 Family - Keil - Describes lower 128-byte RAM use, direct/indirect access, and bit-oriented instruction capabilities. ↩

8. Special Function Register Space: 80H–FFH

The address range 80H–FFH is reserved for Special Function Registers (SFRs).2 These are control and status registers associated with CPU operation and on-chip peripherals.

Typical SFRs include:2

SFRAddressFunction
P080HPort 0 latch
SP81HStack Pointer
DPL82HData Pointer low byte
DPH83HData Pointer high byte
PCON87HPower control
TCON88HTimer control
TMOD89HTimer mode
P190HPort 1 latch
SCON98HSerial control
SBUF99HSerial data buffer
P2A0HPort 2 latch
IEA8HInterrupt enable
P3B0HPort 3 latch
IPB8HInterrupt priority
PSWD0HProgram Status Word
ACCE0HAccumulator
BF0HB register

Not all addresses between 80H and FFH are necessarily implemented in every device, but the standard SFR locations are architecturally defined.2

Some SFRs are also bit-addressable, particularly those whose addresses end in 0H or 8H in the standard map, such as P0, TCON, P1, SCON, P2, IE, P3, IP, PSW, ACC, and B.

Footnotes

  1. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2

  2. C51 Family - Keil - Provides architectural discussion of internal RAM, upper regions, and SFR behavior. ↩ ↩2 ↩3

  3. C51 Family - Keil - Describes lower 128-byte RAM use, direct/indirect access, and bit-oriented instruction capabilities. ↩

  4. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

9. Program Memory in the Standard 8051

The standard 8051 includes 4 KB of on-chip program memory, usually occupying addresses 0000H through 0FFFH in code space.2 Because the Program Counter is 16 bits, the processor can address a total of 64 KB of program memory, from 0000H to FFFFH.2

This leads to an important distinction:

  • On-chip code memory available in standard 8051: 4 KB2
  • Maximum code address space the CPU can address: 64 KB2

If the EA (External Access) pin is held high, the 8051 uses internal ROM for the lower 4 KB and external code memory for addresses beyond 0FFFH if needed.3 If EA is held low, the processor ignores internal ROM and fetches all code from external program memory.2

The signal PSEN is used during reading of external program memory.2

Footnotes

  1. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩ ↩2 ↩3 ↩4 ↩5 ↩6 ↩7

  2. Block Diagram of 8051 Microcontroller - States that internal ROM occupies code memory 0000H-0FFFH in the standard 8051. ↩ ↩2 ↩3

  3. 8051 Hardware Overview - Documents 16-bit PC, EA, PSEN, and the 64 KB code-space map. ↩ ↩2 ↩3 ↩4 ↩5

Standard 8051 Memory Capacity Overview

Comparison of key built-in memory regions in the classic 8051

10. How the 16-bit Program Counter Addresses Program Memory

The Program Counter (PC) is a 16-bit register that holds the address of the next instruction byte to be fetched.2 Because 16 bits can represent:

216=655362^{16} = 65536

the PC can address:

65536 bytes=64 KB65536 \text{ bytes} = 64 \text{ KB}

of code space.2

In normal execution:

  • the PC points to the next code byte,
  • the CPU fetches the instruction byte from program memory,
  • the PC increments automatically after fetch,
  • branch and call instructions load the PC with a new address.2

Thus, while the standard chip contains only 4 KB internal ROM, the architecture itself supports a 64 KB code-space model.2

Footnotes

  1. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩ ↩2 ↩3 ↩4

  2. 8051 Hardware Overview - Documents 16-bit PC, EA, PSEN, and the 64 KB code-space map. ↩ ↩2 ↩3 ↩4

Program Memory Clarifications

11. Integrated Concept Map

The 8051 memory system can be viewed as a layered structure:

This model ties together the course learning goals:

  • separate program and data memory spaces,2
  • internal RAM divided into register banks, bit-addressable RAM, and general-purpose RAM,2
  • PSW-based bank selection,
  • bit-level instructions on selected memory regions,2
  • and 4 KB standard program ROM addressed within a 16-bit code space.3

Footnotes

  1. MICROCONTROLLERS LEARNING OBJECTIVES - Describes Harvard architecture and identifies the 8051 as using separate program and data memories. ↩

  2. ARCHITECTURE OF 8031/8051 MICROCONTROLLER - Explains internal 4 KB ROM, 16-bit PC, EA behavior, and external code memory access. ↩ ↩2

  3. TOPIC NAME-8051 Microcontroller Memory Organization - Details internal RAM layout, register banks, bit-addressable area, and SFR region. ↩ ↩2

  4. Internal RAM organization of 8051 - Gives address ranges for register banks, bit-addressable RAM, and general-purpose RAM. ↩

  5. 80C51 family architecture - PJRC - Explains direct and indirect addressing, register-bank selection, and direct bit operations in RAM and SFR space. ↩

  6. 8051 Instruction Set - Silicon Labs - Highlights Boolean variable operations and confirms bit-addressable memory from 20H to 2FH. ↩

  7. Block Diagram of 8051 Microcontroller - States that internal ROM occupies code memory 0000H-0FFFH in the standard 8051. ↩

  8. 8051 Hardware Overview - Documents 16-bit PC, EA, PSEN, and the 64 KB code-space map. ↩

Knowledge Check

Question 1 of 5
Q1Single choice

Which address range in the standard 8051 internal RAM is reserved for the four register banks?

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