PYQ Analysis — Module 2: The 8051 Architecture

Topic Distribution Analysis

Module 2 is the highest weightage module in the exam, carrying 15–20 marks. Focus on:

High-Weightage Questions (Expected Tomorrow)

Q1: Draw and explain the internal block diagram of 8051 microcontroller. (8 marks)

Answer Overview:

Key functional blocks:

1. CPU — 8-bit processor core with ALU and Control Unit
2. ALU — Performs arithmetic & logical ops; includes Accumulator (A), B register
3. PSW (Program Status Word) — Flags: CY, AC, OV, P, RS1, RS0 (register bank select)
4. Internal RAM — 128 bytes (00H-7FH): Register banks (00-1F), Bit-addressable (20-2F), Scratchpad (30-7F)
5. SFR Space — 80H-FFH (only 21 SFRs defined)
6. ROM — 4 KB internal program memory
7. I/O Ports — 4 ports × 8 bits = 32 I/O pins
8. Timers — 2 × 16-bit timer/counters (T0, T1)
9. Serial Port — Full-duplex UART
10. Interrupt Control — 5 interrupt sources, 2 priority levels

Q2: Explain the Special Function Registers (SFRs) and their address mapping. (5 marks)

SFR space: Upper 128 bytes (80H to FFH) of internal data memory. Only 21 SFRs are defined.

Key SFRs:

Bit-addressable SFRs: Those ending in 0H or 8H (P0, TCON, P1, SCON, P2, IE, P3, IP, PSW, ACC, B)

Q3: Explain the 8051 PSW register with its flag bits. (4 marks)

PSW (Program Status Word) — Address D0H, Bit-addressable

Register Bank Selection (RS1, RS0):

Q4: Compare Port 0, Port 1, Port 2, and Port 3 of the 8051. (5 marks)

Port 3 Alternate Functions:

• P3.0 → RXD (Serial input)
• P3.1 → TXD (Serial output)
• P3.2 → INT0 (External interrupt 0)
• P3.3 → INT1 (External interrupt 1)
• P3.4 → T0 (Timer 0 external input)
• P3.5 → T1 (Timer 1 external input)
• P3.6 → WR (External data memory write strobe)
• P3.7 → RD (External data memory read strobe)

Q5: Explain the memory organization of 8051. (4 marks)

Harvard Architecture — separate program and data memory spaces:

Program Memory (ROM):

• Internal: 4 KB (0000H-0FFFH)
• External: Up to 64 KB via PSEN signal
• EA = 1: Internal ROM (first 4K), then external
• EA = 0: External ROM only

Data Memory (RAM):

• Internal Data Memory (128 bytes — 00H-7FH):
  • Register Banks: 00H-1FH (4 banks × 8 registers = 32 bytes)
  • Bit-addressable: 20H-2FH (16 bytes = 128 bits, addressable individually)
  • Scratchpad: 30H-7FH (80 bytes general purpose)
• SFR Space: 80H-FFH (upper 128 bytes, only 21 SFRs)
• External Data Memory: Up to 64 KB via MOVX instructions

Q6: Explain clock circuit, RESET circuit, and machine cycle. (4 marks)

Clock Circuit:

• Crystal connected between XTAL1 (input) and XTAL2 (output)
• Two 30pF capacitors to ground for stability
• Typical crystal: 12 MHz (exact) or 11.0592 MHz (for serial comm)

Machine Cycle:

• 1 Machine Cycle = 12 Oscillator Periods (clock cycles)
• At 12 MHz: 1 machine cycle = 1 µs
• Most instructions execute in 1 or 2 machine cycles
• MUL/DIV take 4 machine cycles

RESET Circuit:

• Active HIGH reset (min 2 machine cycles)
• RST pin held HIGH via 10 µF cap to Vcc and 10 kΩ resistor to GND
• Power-On Reset: Cap charges through resistor, RST eventually goes LOW

Register states after RESET:

• PC = 0000H, SP = 07H, P0-P3 = FFH (all ports HIGH)
• All SFRs cleared, timers stopped

Q7: Explain timing diagram for external program memory fetch. (5 marks)

ALE (Address Latch Enable):

• Goes HIGH once per machine cycle
• In T1 (first state of machine cycle): ALE = HIGH → address valid on Port 0
• External latch captures address on ALE falling edge

PSEN (Program Store Enable):

• Goes LOW twice per machine cycle for external fetch
• Active during T2, T3, T4 states
• Remains HIGH during internal ROM access

Sequence:

1. T1: ALE HIGH, Address out on P0 (AD0-AD7) and P2 (A8-A15)
2. ALE ↓: External latch (74373) captures lower address byte
3. T2: PSEN ↓ LOW, external ROM places instruction byte on P0 (now data)
4. T3: PSEN ↑ HIGH, CPU reads instruction on rising edge
5. T4: Next cycle begins...

Quick Revision Notes

• ACC (E0H) — Most versatile register, source/destination for most operations
• B (F0H) — Used with ACC for MUL and DIV
• SP = 07H after RESET — Stack starts at 08H (grows upward, pre-increment/post-decrement)
• DPTR — 16-bit: DPH (83H) + DPL (82H), used for external memory and table lookup
• PC (Program Counter) — 16-bit, not an SFR, can hold 0000H-FFFFH (64K range)
• ONLY Port 0 needs external pull-ups for I/O operation
• Port 0 is open-drain, Ports 1-3 have internal pull-ups