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Microprocessor

Memory Device Interfacing

1.25 hours

Learning Goals

  • Understand ROM interfacing requirements: connecting external ROM chips to expand program memory capacity, utilizing PSEN (Program Store Enable) signal for ROM read control, managing address bus for ROM addressing, and recognizing ROM access timing constraints
  • Master RAM interfacing design: connecting external RAM for data memory expansion or program data storage, utilizing RD/WR signals for read/write control, implementing simultaneous address/data bus multiplexing through demultiplexing circuits, and addressing timing requirements
  • Analyze memory address allocation: calculating required address lines for ROM/RAM capacity (16 kB ROM requiring 14 address lines A0-A13, 8 kB RAM requiring 13 address lines A0-A12), understanding address range assignment for device selection
  • Apply address decoding strategies: designing chip select logic for ROM/RAM device selection, recognizing full address decoding vs partial decoding for cost tradeoff, implementing multi-chip memory systems with shared address bus
  • Calculate address ranges: allocating external ROM to address range (e.g., 8000H-BFFFH for 16 kB), allocating external RAM to range (e.g., 8000H-9FFFH for 8 kB), ensuring no address conflicts between memory regions
  • Understand memory timing: analyzing ROM access time requirements (50-200 ns typical) determining wait state necessity, recognizing RAM read/write cycle timing constraints, and implementing wait states when required for slow devices
  • Master memory interface control: coordinating address latch enable (ALE) with external memory decoding, managing read strobe timing relative to data valid window, ensuring write timing for data setup/hold around WR pulse
  • Apply practical memory system design: combining internal and external memory efficiently, managing memory allocation between program and data spaces, recognizing performance impact of external memory access vs internal memory

Memory interfacing is the process of connecting external memory chips to a microprocessor to expand its storage capacity for programs (ROM) and data (RAM). Since a microprocessor like the 8051 or 8085 has a limited internal memory, external expansion is essential for complex applications .

The interface relies on three primary buses:

  1. Address Bus: Unidirectional; identifies the specific memory location.
  2. Data Bus: Bidirectional; carries the actual information between the processor and memory.
  3. Control Bus: Carries signals like RD‾\overline{RD}, WR‾\overline{WR}, and PSEN‾\overline{PSEN} to synchronize the operation.

In many microprocessors, the lower address bits (A0−A7A_0-A_7) and data bits (D0−D7D_0-D_7) are multiplexed on the same pins to save space. A hardware latch (typically 74LS373) is used to separate them using the Address Latch Enable (ALE) signal .

Footnotes

  1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩ ↩2

Memory Interfacing in 8051 Microcontroller Explained

External ROM Interfacing

Read-Only Memory (ROM) is used to store program code. In the 8051 architecture, external ROM is accessed using the Program Store Enable (PSEN‾\overline{PSEN}) signal. When the processor fetches an instruction from external memory, it asserts PSEN‾\overline{PSEN} to activate the ROM's Output Enable (OE‾\overline{OE}) pin .

External RAM Interfacing

Random Access Memory (RAM) provides temporary storage for data variables. Unlike ROM, RAM requires two control signals:

  • RD‾\overline{RD} (Read): Asserted to read data from RAM.
  • WR‾\overline{WR} (Write): Asserted to store data into RAM.

These signals are typically mapped to Port 3 pins (P3.7 for RD‾\overline{RD} and P3.6 for WR‾\overline{WR}) in the 8051 .

Footnotes

  1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩ ↩2

Designing a Memory Interface

  1. 1
    Step 1

    Calculate the number of address lines required using the formula 2n=Capacity2^n = \text{Capacity}. For a 16 kB ROM, 214=163842^{14} = 16384, so 14 address lines (A0−A13A_0 - A_{13}) are needed. For an 8 kB RAM, 13 lines (A0−A12A_0 - A_{12}) are required .

    Footnotes

    1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩

  2. 2
    Step 2

    Assign a starting address and calculate the end address. For a 16 kB ROM starting at 8000H8000H: End Address=8000H+(4000H−1)=BFFFH\text{End Address} = 8000H + (4000H - 1) = BFFFH. Ensure no two devices overlap in the address space to avoid bus contention .

    Footnotes

    1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩

  3. 3
    Step 3

    Use the remaining high-order address lines (e.g., A14,A15A_{14}, A_{15}) to create a Chip Select signal. This ensures the memory chip is only active when the processor targets its specific range .

    Footnotes

    1. Memory Interfacing in 8085 | Wait State Generator - Technical article on absolute vs. linear decoding and wait states. ↩

  4. 4
    Step 4

    Connect the multiplexed AD0−AD7AD_0-AD_7 to a latch, connect the control signals (PSEN‾\overline{PSEN} for ROM, RD‾/WR‾\overline{RD}/\overline{WR} for RAM), and tie the Address/Data buses to the respective pins on the memory chip .

    Footnotes

    1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩

Demultiplexing with ALE

Always remember that the ALE (Address Latch Enable) signal is active high. It pulses during the first half of a machine cycle to indicate that valid address bits are present on the multiplexed bus. Use this pulse to trigger the 74LS373 latch to 'hold' the address for the remainder of the cycle .

Footnotes

  1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩

SignalFunctionConnection
PSEN‾\overline{PSEN}Program Store EnableROM OE‾\overline{OE}
A0−A15A_0 - A_{15}Address LinesROM Address Pins
D0−D7D_0 - D_7Data BusROM Data Pins
EA‾\overline{EA}External AccessTied to GND for external ROM

Address Line Requirements vs. Memory Size

Number of address lines (n) required for common memory capacities

Address Decoding Strategies

Address Conflicts

Never allow two memory devices to have overlapping address ranges. If both chips are selected simultaneously, they will both attempt to drive the data bus, leading to bus contention. This can cause data corruption and potentially damage the hardware .

Footnotes

  1. Memory and I/O Interfacing - 8051 - Detailed technical guide on ROM/RAM interfacing and decoding. ↩

Knowledge Check

Question 1 of 4
Q1Single choice

Which signal is specifically used by the 8051 to enable the output of an external program ROM?

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