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Microprocessor

Memory and I/O Expansion Buses

1 hour

Learning Goals

  • Understand external bus architecture: recognizing 16-bit address bus (A0-A15 from Port 0 lower bits and Port 2) for accessing up to 64 kB external memory, 8-bit data bus (Port 0 for multiplexed address/data transmission), and separate program and data memory spaces
  • Master address/data bus multiplexing: understanding Port 0 dual functionality transmitting address during ALE pulse then data during read/write, recognizing ALE (Address Latch Enable) signal synchronization, and analyzing demultiplexing circuitry with external latch (74373 or similar)
  • Explain bus demultiplexing: utilizing external latch triggered by ALE signal to capture and hold address, separating multiplexed AD0-AD7 into address and data components, and applying demultiplexing for external memory access
  • Analyze expansion memory requirements: calculating address space requirements for 16 kB ROM and 8 kB RAM expansion, understanding address range allocation (ROM: external program memory, RAM: external data memory), and recognizing memory decode requirements
  • Apply control signal integration: coordinating PSEN (Program Store Enable) for external ROM access, utilizing RD/WR for external data memory access, managing EA pin for external/internal memory selection, and integrating timing synchronization
  • Understand memory interface timing: analyzing address setup and hold times relative to ALE pulse, recognizing data valid times relative to read strobes, and ensuring timing compliance for interfaced devices
  • Design external memory configurations: calculating chip select (CS) signals for multiple memory devices, managing address decoding for partial address utilization, and optimizing memory layout for efficient access patterns
  • Compare Von Neumann vs Harvard bus organization: understanding separate program/data memory benefits in Harvard architecture, recognizing potential address space conflicts, and managing dual-bus requirements in external expansion

In microprocessor systems, specifically the 8051 family, the internal memory is often insufficient for complex applications. To overcome this, the architecture provides a mechanism for External Memory and I/O Expansion. This is achieved through a 16-bit address bus and an 8-bit data bus, allowing the processor to address up to 64 KB of external program memory and 64 KB of external data memory .

The 8051 uses a multiplexed bus system to conserve pin count. Port 0 serves a dual role: it transmits the lower 8 bits of the address (A0−A7A_0-A_7) and then switches to act as the 8-bit data bus (D0−D7D_0-D_7). Port 2 provides the upper 8 bits of the address (A8−A15A_8-A_{15}) .

Footnotes

  1. 8051 Architecture and PSEN Overview - Overview of external memory interfacing and pin functions. ↩

  2. 8051 Microcontroller Architecture PDF - Details on Port 0/2 multiplexing and ALE functionality. ↩

Demultiplexing of Address and Data Lines of 8051

Harvard Architecture vs. Von Neumann

The 8051 utilizes a Harvard Architecture, which physically separates the storage and signal pathways for instructions (Program Memory) and data (Data Memory) . This differs from the Von Neumann architecture, where a single bus is used for both.

Key Benefits of 8051 Harvard Organization:

  • Simultaneous Access: While the CPU is fetching an instruction from ROM, it can theoretically prepare for a data operation in RAM.
  • Address Space Overlap: Because the control signals differ (PSEN‾\overline{PSEN} for ROM vs. RD‾/WR‾\overline{RD}/\overline{WR} for RAM), the system can have a Program Memory address 0000H0000H and a Data Memory address 0000H0000H without conflict .

Footnotes

  1. Harvard vs Von Neumann Architecture - Comparison of memory organization models. ↩

  2. 8051 Interfacing and Applications - Technical details on memory decoding and timing. ↩

Memory Space Comparison (8051)

Maximum Addressable External Memory via Expansion Buses

Bus Demultiplexing Process

  1. 1
    Step 1

    The CPU places the lower 8 bits of the address (A0−A7A_0-A_7) on Port 0 and the upper 8 bits (A8−A15A_8-A_{15}) on Port 2.

  2. 2
    Step 2

    The CPU generates a high-to-low pulse on the ALE (Address Latch Enable) pin. This signal indicates that the data currently on Port 0 is a valid address.

  3. 3
    Step 3

    An external latch (typically a 74LS373) captures the A0−A7A_0-A_7 bits from Port 0 while ALE is high. When ALE goes low, the latch holds these bits constant for the remainder of the machine cycle.

  4. 4
    Step 4

    Port 0 is now freed from its address duties. The CPU uses it to either read data from or write data to the external device (D0−D7D_0-D_7), while the 74373 continues to provide the lower address bits to the memory chip.

The Role of the EA Pin

The External Access (EA) pin is critical for memory expansion. If EA‾\overline{EA} is tied to VCCV_{CC}, the CPU starts executing from internal ROM (0000H−0FFFH0000H-0FFFH). If EA‾\overline{EA} is tied to GNDGND, the CPU ignores internal ROM and fetches all instructions from external memory .

Footnotes

  1. 8051 Architecture and PSEN Overview - Overview of external memory interfacing and pin functions. ↩

Control Signal Integration

To manage the external buses, the 8051 relies on four primary control signals:

  1. PSEN‾\overline{PSEN} (Program Store Enable): This is the read strobe for external Program Memory. It connects to the OE‾\overline{OE} (Output Enable) pin of the ROM.
  2. RD‾\overline{RD} (Read): The read strobe for external Data Memory (RAM).
  3. WR‾\overline{WR} (Write): The write strobe for external Data Memory (RAM).
  4. ALE (Address Latch Enable): Used to demultiplex the address and data on Port 0 .

Footnotes

  1. 8051 Microcontroller Architecture PDF - Details on Port 0/2 multiplexing and ALE functionality. ↩

To read from external program memory, the MOVC (Move Constant) instruction is used.

1MOV DPTR, #2000H ; Load address
2CLR A            ; Clear Accumulator
3MOVC A, @A+DPTR  ; Fetch byte from ROM address 2000H

Note: This triggers the PSEN signal.

Designing Memory Configurations

When expanding memory, we must calculate the address lines required and design the decoding logic.

Example: Interfacing 16 KB ROM and 8 KB RAM

  1. 16 KB ROM:
    • Size: 16×1024=16,38416 \times 1024 = 16,384 bytes.
    • Address lines needed: 214=16,3842^{14} = 16,384, so A0A_0 to A13A_{13}.
    • Address Range: 0000H0000H to 3FFFH3FFFH.
  2. 8 KB RAM:
    • Size: 8×1024=8,1928 \times 1024 = 8,192 bytes.
    • Address lines needed: 213=8,1922^{13} = 8,192, so A0A_0 to A12A_{12}.
    • Address Range: Typically mapped to start after ROM or at a specific boundary, e.g., 8000H8000H to 9FFFH9FFFH.

Address Decoding: To prevent bus contention, we use a decoder (like the 74LS138) connected to the higher address lines (A13−A15A_{13}-A_{15}) to generate Chip Select (CS‾\overline{CS}) signals for each memory chip.

Footnotes

  1. 8051 Memory Interfacing Guide - Practical steps for interfacing ROM and RAM. ↩

Bus Contention and Timing

Ensure that the memory access time is compatible with the 8051 clock frequency. If the memory is too slow, the data might not be valid when the RD‾\overline{RD} strobe is active, leading to corrupted data reads .

Footnotes

  1. 8051 Interfacing and Applications - Technical details on memory decoding and timing. ↩

Expansion Troubleshooting and Logic

Knowledge Check

Question 1 of 4
Q1Single choice

Which signal is used to capture the lower 8 bits of the address from the multiplexed Port 0?

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