PYQ Analysis — Module 3: Instruction Set and Programming

Topic Distribution Analysis

Module 3 is the second highest weightage module, carrying 12–18 marks. Focus on:

High-Weightage Questions (Expected Tomorrow)

Q1: List and explain all 7 addressing modes of 8051 with examples. (6 marks)

1. Immediate Addressing — Data is part of the instruction itself.

• Syntax: # prefix denotes immediate data
• Example: MOV A, #35H — Load 35H into accumulator
• 2-byte instruction: opcode + immediate data
• Used for: Loading constants

2. Register Addressing — Operand is in one of R0–R7 registers.

• Syntax: Register name (R0–R7)
• Example: MOV A, R0 — Copy R0 into A
• Fastest mode (no memory access for operand)
• Uses active register bank (selected by RS1, RS0 in PSW)

3. Direct Addressing — Operand address is explicitly given.

• Syntax: Memory address (00H–FFH)
• Example: MOV A, 0FH — Load from RAM address 0FH
• Can access: Internal RAM (00H-7FH) and SFRs (80H-FFH)

4. Register Indirect Addressing — Register holds the address of data.

• Syntax: @ prefix (only R0, R1 can be pointer registers)
• Example: MOV A, @R0 — Load from address stored in R0
• DPTR can also be used for 16-bit indirect (MOVX)

5. Relative Addressing — Used in branch instructions.

• Address = PC + offset (signed 8-bit: -128 to +127)
• Example: SJMP LABEL — Jump to LABEL relative to current PC

6. Indexed Addressing — PC or DPTR + Accumulator forms address.

• Example: MOVC A, @A+DPTR — Read from program memory at A+DPTR
• Used for: Lookup tables in program memory

7. Bit Addressing — Access individual bit locations.

• Syntax: bit address or dot notation
• Example: SETB P1.0 — Set bit 0 of Port 1
• Only for: Bit-addressable RAM (20H-2FH) and SFRs ending in 0H/8H

Q2: Classify 8051 instructions and give 2 examples of each type. (5 marks)

Q3: Trace the execution of the following program and show register/flags after each step. (5 marks)

1MOV A, #35H        ; A = 35H, Flags unchanged
2ANL A, #0FH        ; A = 35H AND 0FH = 05H, P flag = 0 (even 1s in 05H)
3ORL A, #30H        ; A = 05H OR 30H = 35H, P flag determined
4XRL A, #FFH        ; A = 35H XOR FFH = CAH, P flag determined
5CPL A              ; A = NOT CAH = 35H, No flags affected

Step-by-step trace:

Key observation: CPL does NOT affect any flags (CY, AC, OV, P remain unchanged).

Q4: Explain relative addressing. A JNC instruction is at address 1000H. The branch target is at 1005H. Calculate the relative address. (3 marks)

Relative addressing: The jump offset is an 8-bit signed number (-128 to +127).

Calculation:

• JNC instruction at address 1000H is 2 bytes: [opcode] [relative_offset]
• After fetching, PC = 1000H + 2 = 1002H (points to next instruction)
• Relative offset = Target - PC = 1005H - 1002H = 03H
• So the 2nd byte of the instruction = 03H

Formula: Offset = Target_Address − (Branch_Instruction_Address + 2)

Q5: Write an 8051 assembly program to convert odd parity to even parity. (5 marks)

1; Assume number to convert is in R0
2; Output in R0 with even parity
3
4CONVERT_PARITY:
5    MOV A, R0          ; Load the number
6    MOV R1, A          ; Save original
7    CLR C              ; Clear carry for counting
8    MOV R2, #08H       ; Counter = 8 bits
9    
10COUNT_ONES:
11    RRC A              ; Rotate right through carry
12    JNC SKIP_INC       ; If CY = 0, don't increment
13    INC R2             ; Count the 1
14    
15SKIP_INC:
16    DJNZ R2, COUNT_ONES ; Loop for all 8 bits
17    
18; R2 now has count of 1s
19; Check if R2 is odd or even
20    MOV A, R2
21    ANL A, #01H        ; Check LSB
22    JZ  PARITY_EVEN    ; If LSB = 0, count is even
23    
24; Odd count — need to set parity bit to make it even
25    MOV A, R1
26    ORL A, #80H        ; Set MSB as parity bit
27    SJMP DONE
28    
29PARITY_EVEN:
30    MOV A, R1
31    ANL A, #7FH        ; Clear MSB (even parity: MSB = 0)
32    
33DONE:
34    MOV R0, A          ; Result back to R0
35    RET

Q6: Explain PUSH and POP instructions with stack behavior. (3 marks)

PUSH:

• Pre-increments SP, then copies data to stack
• Example: PUSH ACC — SP ← SP+1, then (SP) ← ACC
• If SP = 07H: SP becomes 08H, then ACC stored at 08H

POP:

• Copies data from stack to destination, then post-decrements SP
• Example: POP B — B ← (SP), then SP ← SP-1
• If SP = 09H: B loaded from 09H, then SP = 08H

Stack discipline: LIFO (Last In, First Out)

Q7: What is the effect of CPL A on flags? (2 marks)

CPL A (Complement Accumulator) — Flips all 8 bits of ACC.

Flag effect: NONE of the flags are affected (CY, AC, OV, P remain unchanged).

This contradicts many students' intuition that complementing should affect parity.

Q8: Explain 8051 C programming features for embedded systems. (4 marks)

Key features:

1. Data Types: char (8-bit), int (16-bit), bit (single bit)
2. Register Variables: register char x — forces variable into R0-R7
3. Bit Fields: Compact flag storage in structures
4. Interrupts: void timer0(void) interrupt 1 — ISR with register bank switching
5. Memory Models: Small (data ≤128B), Compact, Large
6. Inline Assembly: #pragma asm ... #pragma endasm for performance-critical sections

Quick Revision Notes

• MOV A, #35H = Immediate (data in instruction) vs MOV A, 35H = Direct (from address 35H)
• MOVC A, @A+DPTR — Read program memory (table lookup)
• MOVX A, @DPTR — Read external data memory
• CJNE — Compare and Jump if Not Equal (affects CY flag)
• DJNZ — Decrement and Jump if Not Zero (loop control)
• RET — Return from subroutine; RETI — Return from interrupt (re-enables interrupts)
• XRL A, A — Clears ACC (result = 0), P flag becomes 0
• PUSH = pre-increment, POP = post-decrement (opposite of 8085!)
• SJMP = Short Jump (-128 to +127 bytes), LJMP = Long Jump (full 64K), AJMP = Absolute Jump (2K page)
• JNC = Jump if No Carry (CY=0), JC = Jump if Carry (CY=1)