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Microprocessor

Control Signals and Memory Wait States

1 hour

Learning Goals

  • Understand control signal functions: ALE (Address Latch Enable) pulse for address latching in demultiplexing, PSEN (Program Store Enable) for external program memory read operations, RD (Read strobe) for external data memory read, WR (Write strobe) for external data memory write, and EA (External Access) for memory selection
  • Analyze signal timing relationships: recognizing ALE pulse timing within machine cycle, understanding PSEN assertion during external fetch operations, analyzing RD/WR pulse width and timing relative to data valid window, and managing setup/hold constraints
  • Master ALE signal demultiplexing: using ALE pulse to trigger external latch capturing Port 0 address during first half of machine cycle, releasing address to external decode logic for chip selection, and understanding demultiplexing recovery time
  • Explain wait state insertion: inserting wait states (extra machine cycles) for slow memory devices requiring extended access time, recognizing WAIT pin functionality for dynamic wait state generation, and managing wait state overhead on system performance
  • Apply memory timing synchronization: analyzing memory access sequences with wait states, ensuring data valid before RD strobe termination, validating setup time before write strobe capture, and optimizing performance within timing constraints
  • Understand EA pin control: EA pin forcing external program memory access when LOW, enabling internal ROM when HIGH, and managing mixed internal/external program memory configurations for flexible system design
  • Analyze device-specific wait states: calculating wait states required for various ROM/RAM devices (e.g., 70ns access time devices requiring 1-2 wait states at 12 MHz operation), optimizing wait state selection for cost/performance tradeoff
  • Compare different bus modes: recognizing standard bus operation without wait states, analyzing burst mode access patterns for sequential memory, and understanding alternate modes for special device interfacing

In microprocessor systems, the synchronization between the Central Processing Unit (CPU) and external memory or I/O devices is managed through a set of dedicated control signals. These signals ensure that data is placed on the bus only when the address is stable and that the correct device is activated for the intended operation (read or write) .

The primary control signals in a typical 8-bit architecture (such as the 8051) include:

  • ALE (Address Latch Enable): A pulse used to demultiplex the address and data bus.
  • PSEN (Program Store Enable): The "read" strobe specifically for external program memory.
  • RD (Read) & WR (Write): Strobes for external data memory/IO operations.
  • EA (External Access): A hardware strap that determines whether the CPU fetches instructions from internal or external memory.

The Timing Framework

Microprocessor operations are divided into Machine Cycles. A machine cycle consists of multiple states (S-states), where specific control signals are asserted at precise intervals to meet the setup and hold time requirements of memory chips .

Footnotes

  1. PINS AND SIGNALS OF 8031/8051 MICROCONTROLLER - Detailed overview of control pins and their logical functions. ↩

  2. 8051 Hardware Overview - Summary of the MCS-51 architecture and timing. ↩

Memory Interfacing in 8051 Microcontroller Explained

ALE and Bus Demultiplexing

To reduce pin count, many microprocessors multiplex the lower byte of the address (A0−A7A_0-A_7) with the data bus (D0−D7D_0-D_7) on the same pins (e.g., Port 0 in 8051). ALE (Address Latch Enable) is the key to separating these two.

When ALE is high, the pins carry the address. As ALE transitions from high to low, it triggers an external latch (like the 74LS373) to capture and "hold" the address for the remainder of the cycle, freeing the CPU pins to act as a data bus .

Footnotes

  1. Demultiplexing the Bus AD7 – AD0 - Technical guide on using the 74LS373 with the ALE signal. ↩

The Demultiplexing Process

  1. 1
    Step 1

    The CPU places the lower 8 bits of the address (A0−A7A_0-A_7) on Port 0 and the higher 8 bits (A8−A15A_8-A_{15}) on Port 2.

  2. 2
    Step 2

    The CPU pulses the ALE pin high. This signal is connected to the 'Enable' (G) pin of an external 74LS373 transparent latch.

  3. 3
    Step 3

    As ALE goes low, the 74LS373 captures the state of Port 0. The latch now provides a stable A0−A7A_0-A_7 to the memory's address pins.

  4. 4
    Step 4

    With the address safely latched externally, the CPU transitions Port 0 to a high-impedance state (for Read) or outputs data (for Write).

ALE Frequency

In a standard 8051, ALE pulses at a frequency of 1/61/6 the oscillator frequency. Even when no external memory is accessed, ALE continues to pulse, making it a useful clock source for external circuits.

Used exclusively for fetching instructions from External Program Memory. It is active low. During a fetch, PSEN is asserted twice per machine cycle. It connects to the Output Enable (OE) pin of the EPROM/ROM.

Wait States and Timing Synchronization

Not all memory devices are fast enough to respond within the standard CPU machine cycle. If a memory device's Access Time (TaccT_{acc}) is greater than the time the CPU provides between the address becoming stable and the RD strobe ending, the CPU will read "garbage" data.

Wait States are extra machine cycles inserted into the bus cycle to stretch the control signals, giving slow devices more time to respond .

Wait States (N)=⌈Tacc−TavailableTcycle⌉Wait\ States\ (N) = \lceil \frac{T_{acc} - T_{available}}{T_{cycle}} \rceil

For example, if a 12 MHz system provides a 300ns window but the memory requires 450ns, at least one wait state must be inserted to extend the window by one clock period (1/12μs≈83.3ns1/12 \mu s \approx 83.3ns) or one full machine cycle depending on the architecture.

Footnotes

  1. Wait state - Wikipedia - General definition and logic of wait state insertion in microprocessors. ↩

System Throughput vs. Wait States

Impact of Wait States on effective instructions per second

Setup and Hold Constraints

When interfacing, ensure that the Data Setup Time (time data is valid before RD/WR rises) and Data Hold Time (time data remains valid after strobe) meet the CPU's datasheet specifications to prevent bus contention or data corruption.

The EA Pin and Memory Selection

Knowledge Check

Question 1 of 3
Q1Single choice

Which signal is used to trigger an external latch to separate the address from the data bus?

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