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Architecture of x86 Processors: Registers, Addressing Modes, and Instruction Format

Architecture of x86 Processors: Registers, Addressing Modes, and Instruction Format

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Nov 4, 2026

The x86 family is a CISC architecture whose execution model can be understood as: a microarchitectural core executes decoded instructions, while the architectural state (registers, flags, control registers, segment/base/limit state, and memory addressing rules) defines program-visible behavior. At the instruction boundary, the CPU:

  • fetches an instruction stream from memory using the current instruction pointer,
  • decodes prefixes + opcode + ModR/M(+SIB)+displacement+immediate,
  • computes effective addresses (EA) using x86 addressing modes,
  • reads/writes operands via registers and memory, and
  • updates architectural state (including flags).

A helpful mental model is that x86 “architecture rules” live in three interacting layers: (1) register file and flags, (2) segmentation/base-index addressing for effective addresses, and (3) variable-length instruction encoding that drives decoding. 3

Key x86 concepts (for this section)

  • Effective Address (EA)
  • ModR/M
  • SIB
  • Prefix

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (register overview, general instruction decoding concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  3. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

x86 instruction encoding overview (prefix, opcode, ModR/M, SIB)

Architectural register sets: what “registers” mean on x86

x86 exposes multiple register classes. Even if microarchitecture implements them differently internally, the architectural programmer-visible contract is what matters for understanding instruction semantics.

Common register groups:

  1. General-purpose registers (GPRs): arithmetic/data registers (e.g., EAX/RAX, EBX/RBX, ECX/RCX, EDX/RDX, ESI/RSI, EDI/RDI, EBP/RBP, ESP/RSP) 2
  2. Instruction pointer: EIP (32-bit) or RIP (64-bit)
  3. Flags register: EFLAGS/RFLAGS contains condition codes and control flags
  4. Control registers: CR0–CR4 (enable/disable features, paging, protection)
  5. Debug registers: DR0–DR7 (hardware breakpoints/watchpoints)
  6. Segment registers (legacy but still architecturally relevant): CS, DS, ES, SS, FS, GS with base/limit semantics in protected/compatibility modes

To avoid mixing concepts: segment registers primarily participate in address translation, while general-purpose registers primarily supply operand values and participate in effective address arithmetic.

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (register overview, general instruction decoding concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (RIP and flags/general architectural state) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩ ↩2 ↩3

  3. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3 (control/debug register descriptions) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩ ↩2

  4. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

General-purpose registers and aliasing (32-bit vs 64-bit)

x86 uses register families with architectural aliases:

  • In 32-bit mode, registers are typically named EAX, EBX, ….
  • In 64-bit mode, they become RAX, RBX, ….
  • Many “lower 32-bit” operations have implicit zero-extension behavior on x86-64 (this affects how flags and dependencies behave).

This section focuses on architecture-level understanding of how registers map into the instruction format operands and address generation.

Examples of register naming (conceptual):

  • GPR
  • RIP
  • EFLAGS
  • RFLAGS

(Precise alias behaviors are specified in Intel/AMD manuals; the key takeaway for instruction format is that operand-size and addressing-size prefixes determine which register widths are used for a given instruction encoding.) 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (register overview, general instruction decoding concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (RIP and flags/general architectural state) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Flags: where the CPU records results

Condition codes are stored in EFLAGS/RFLAGS, while other bits control execution behavior. For the course goal here, you should know that instruction semantics often depend on flags and that many arithmetic/logic instructions both compute results and update flags.

Key flags concepts:

  • CF
  • ZF
  • SF
  • OF

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (RIP and flags/general architectural state) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Segment registers and how they relate to addressing

Legacy segmentation uses segment selectors held in segment registers, combined with an offset to form a linear address (in protected mode). Modern x86-64 uses a simplified view for many code/data accesses, but architectural rules and segment override prefixes still exist.

  • Segment Override Prefix

Understanding segment override is crucial because the instruction encoding includes prefix bytes that affect the translation path of memory operands.

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩ ↩2

Addressing modes: how x86 computes memory operands

x86 memory operands are described by encoding fields inside the instruction, most notably ModR/M and often SIB in 32/64-bit addressing.

Effective address formula (core idea)

A common x86 EA form can be represented as:

EA=Base+(Index×Scale)+DisplacementEA = Base + (Index \times Scale) + Displacement

Where:

  • Base and Index come from register fields (or may be absent depending on encoding),
  • Scale is typically one of 1,2,4,81,2,4,8 (encoded compactly),
  • Displacement is an immediate value inside the instruction stream.

The exact availability of components (e.g., index absent, base omitted) depends on the ModR/M and SIB encodings.

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Compute an x86 effective address from instruction bytes

  1. 1
    Step 1

    From the opcode and ModR/M/reg fields, determine which operand(s) are registers and which are memory references.

  2. 2
    Step 2

    Read any prefix bytes (e.g., segment override, address-size override). These affect which addressing rules apply.

    Footnotes

    1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  3. 3
    Step 3

    Use ModR/M fields to determine: (a) whether a memory EA is present, (b) the addressing form, and (c) the displacement size (none/8/32).

    Footnotes

    1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  4. 4
    Step 4

    If the addressing form requires it, decode SIB to extract Scale, Index, and Base register selections.

    Footnotes

    1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  5. 5
    Step 5

    Read displacement bytes (and other immediate bytes, if required) from the instruction stream.

  6. 6
    Step 6

    Apply the x86 EA arithmetic rules implied by the decoded fields.

  7. 7
    Step 7

    If a segment override is present or the default segment applies, compute the translated address using architectural segment/translation rules.

    Footnotes

    1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Common addressing-mode patterns (conceptual mapping)

Below is a simplified mapping between common assembly forms and the underlying encoded ingredients.

Assembly-like form (conceptual)Encoded ingredients (high-level)Notes
[base+disp][base + disp]ModR/M selects EA with Base; displacement may be 8/32Index absent
[base+index∗scale+disp][base + index*scale + disp]ModR/M + SIB provide base/index/scale; displacement addedMost general base-index form
[index∗scale+disp][index*scale + disp]Base may be encoded as absent depending on ModR/M/SIBRequires careful encoding rules
[abs_disp][abs\_disp] (32-bit absolute in some modes)Displacement as address, no base/indexDepends on mode and encoding

(Exact encoding legality depends on mode and specific opcode operand type; the manuals specify the ModR/M and SIB decoding rules.)

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Address-size and operand-size effects

x86 includes prefixes that can override default sizes:

  • Address-Size Prefix
  • Operand-Size Prefix

This matters because the instruction format uses different decoding paths depending on these sizes, which in turn determines whether SIB is used and how registers are selected for effective address computation. 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (register overview, general instruction decoding concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Instruction format: variable-length encoding anatomy

x86 instructions are variable-length. Decoding is driven by:

  1. Prefixes (repeatable categories; order rules apply),
  2. Opcode (1 or more bytes; often determines operand structure),
  3. ModR/M byte (when the opcode expects register/memory operand),
  4. SIB byte (when addressing needs base+index+scale in certain modes),
  5. Displacement (0, 8-bit, or 32-bit depending on addressing form),
  6. Immediate data (optional and opcode-dependent).

Prefix categories that matter for this course

Typical categories include:

  • segment override prefix (affects memory translation),
  • operand-size override prefix,
  • address-size override prefix,
  • and sometimes additional prefixes for specific instruction groups. 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

How to read instruction bytes (byte-level “grammar”)

A generic decode flow can be expressed as:

  1. Read zero or more prefixes.
  2. Read opcode byte(s).
  3. Determine whether an operand encoding byte is needed.
  4. If needed, read ModR/M:
    • Extract mod (addressing mode / displacement presence),
    • extract reg (register operand extension),
    • extract r/m (register or memory addressing selector).
  5. If the addressing form calls for it, read SIB:
    • Extract scale, index, base.
  6. Read displacement if indicated by mod.
  7. Read immediate if specified by the opcode form.

This is the core mechanism that connects instruction format to addressing modes. 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

ModR/M and SIB: why they exist

  • ModR/M compactly encodes: (a) which register (or memory EA) is referenced and (b) which operand-extension field is used by the opcode.
  • SIB extends the addressing vocabulary to support base+index*scale efficiently.

Therefore, “understanding x86 architecture” for a student means connecting these fields to effective address computation.

Key fields:

  • Mod
  • R/M
  • Scale
  • Index
  • Base

(These interpretations are defined by x86 instruction encoding rules.)

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

From bytes to operands (execution-visible pipeline)

Read prefixes

Decode start

Identify overrides (segment/operand-size/address-size) that affect how the rest is interpreted. "

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Read opcode

Next

Opcode determines instruction semantics and whether ModR/M and/or immediates are present. "

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (register overview, general instruction decoding concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Parse ModR/M

Then

Select register vs memory addressing and determine displacement size class. "

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Parse SIB

If needed

Decode Scale/Index/Base for complex effective addresses. "

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Compute EA and execute

Finally

Compute EA, translate address, read/write operands, then update register/flags state. 2"

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (RIP and flags/general architectural state) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Pro Tip: decode in a fixed order

When manually decoding x86, always parse in order: prefixes → opcode → ModR/M → SIB → displacement → immediate. This prevents common mistakes where you mis-read later bytes as earlier fields.

Warning: address-size vs operand-size are different

Address-size override changes how effective addresses are formed; operand-size override changes the width of the data operands. Confusing them leads to incorrect EA arithmetic or incorrect register width.

Visualizing the instruction layout

A simplified diagram for a ModR/M+SIB memory operand case:

Instruction encoding is therefore the “bridge” between the architectural rules for effective addressing and the programmer-visible assembly syntax. 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Summary map: architecture parts you must connect

  • Registers: define operand sources/targets and control behavior (including flags, control/debug registers). 2
  • Addressing modes: determine EA = Base + Index*Scale + Displacement.
  • Instruction format: uses prefixes + opcode + ModR/M (+SIB) + displacement/immediate to drive decoding. 2

Footnotes

  1. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (RIP and flags/general architectural state) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  2. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3 (control/debug register descriptions) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

  3. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (ModR/M, SIB, effective address computation) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩ ↩2

  4. Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 (segment override/prefix and segmentation/translation concepts) - https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html ↩

Knowledge Check

Question 1 of 4
Q1Single choice

In the x86 instruction encoding, which component most directly encodes the addressing mode for a memory operand (including whether a displacement is present)?

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