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Speedup and MIPS for a 5-Stage Pipelined Upgrade with Reduced Clock

Speedup and MIPS for a 5-Stage Pipelined Upgrade with Reduced Clock

Verified Sources
Nov 4, 2026

A processor’s execution time for a “typical program” can be modeled (at the level of this problem) as proportional to:

  • Instruction count (for a fixed program): NN
  • Average CPI: CPI\text{CPI}
  • Clock rate: ff (cycles per second)

So, a simple performance model is:

T=N⋅CPIfT = \frac{N \cdot \text{CPI}}{f}

For the non-pipelined processor:

  • Clock rate: f1=2.5 GHzf_1 = 2.5\ \text{GHz}
  • Average CPI: CPI1=4\text{CPI}_1 = 4

For the pipelined processor (5-stage pipeline), we use the standard assumption for ideal pipelining on a typical program: Pipeline throughput improves to IPC ≈ 1 (i.e., CPI drops to about 1). Thus:

  • CPI2≈1\text{CPI}_2 \approx 1
  • Clock rate reduced to f2=2 GHzf_2 = 2\ \text{GHz} due to internal pipeline delays (e.g., latch delay).

Pipelining: Throughput, CPI, and Speedup (core ideas)

Compute speedup for a typical program

  1. 1
    Step 1

    Using T=N⋅CPIfT = \frac{N\cdot\text{CPI}}{f} and the same program (NN cancels), compute T1T2=CPI1/f1CPI2/f2=CPI1⋅f2CPI2⋅f1\frac{T_1}{T_2} = \frac{\text{CPI}_1/f_1}{\text{CPI}_2/f_2} = \frac{\text{CPI}_1\cdot f_2}{\text{CPI}_2\cdot f_1}.

  2. 2
    Step 2

    Use CPI1=4\text{CPI}_1=4, f1=2.5 GHzf_1=2.5\ \text{GHz}, CPI2≈1\text{CPI}_2\approx 1, f2=2 GHzf_2=2\ \text{GHz}, giving Speedup=4⋅21⋅2.5\text{Speedup} = \frac{4\cdot 2}{1\cdot 2.5}.

  3. 3
    Step 3

    Speedup =82.5=3.2= \frac{8}{2.5} = 3.2.

  4. 4
    Step 4

    A speedup of 3.2×3.2\times means the upgraded pipelined processor completes the same typical program in about 13.2\frac{1}{3.2} the time.

(a) Speedup achieved

S=fracT1T2=fractextCPI1cdotf2textCPI2cdotf1=frac4cdot21cdot2.5=3.2S = \\frac{T_1}{T_2} = \\frac{\\text{CPI}_1\\cdot f_2}{\\text{CPI}_2\\cdot f_1} = \\frac{4\\cdot 2}{1\\cdot 2.5} = 3.2

So the typical-program speedup is:

S≈3.2×\boxed{S \approx 3.2\times}

Typical-program assumption for CPI in pipelines

For many textbook pipeline speedup problems, the key assumption is steady-state ideal throughput on a typical program, giving CPI2≈1\text{CPI}_2\approx 1 for a non-stalling pipeline.

Compute MIPS rate for each processor

  1. 1
    Step 1

    MIPS is 10610^6 instructions per second: MIPS=Instructions/sec106=fCPI⋅106\text{MIPS} = \frac{\text{Instructions/sec}}{10^6} = \frac{f}{\text{CPI}\cdot 10^6}.

  2. 2
    Step 2

    For processor 1: MIPS1=2.5×1094⋅106\text{MIPS}_1 = \frac{2.5\times 10^9}{4\cdot 10^6}.

  3. 3
    Step 3

    MIPS1=2.54×103=0.625×103=625\text{MIPS}_1 = \frac{2.5}{4}\times 10^3 = 0.625\times 10^3 = 625.

  4. 4
    Step 4

    For processor 2: MIPS2=2×1091⋅106\text{MIPS}_2 = \frac{2\times 10^9}{1\cdot 10^6}.

  5. 5
    Step 5

    MIPS2=2×103=2000\text{MIPS}_2 = 2\times 10^3 = 2000.

  6. 6
    Step 6

    The MIPS ratio is 2000625=3.2\frac{2000}{625}=3.2, consistent with the speedup.

(b) MIPS rate for each processor

Processor 1 (non-pipelined):

MIPS1=2.5×1094×106=625\text{MIPS}_1 = \frac{2.5\times 10^9}{4\times 10^6} = 625 MIPS1=625 MIPS\boxed{\text{MIPS}_1 = 625\ \text{MIPS}}

Processor 2 (5-stage pipelined, reduced clock):

MIPS2=2×1091×106=2000\text{MIPS}_2 = \frac{2\times 10^9}{1\times 10^6} = 2000 MIPS2=2000 MIPS\boxed{\text{MIPS}_2 = 2000\ \text{MIPS}}

Performance comparison (typical program)

Using CPI model and given clock rates

Common pitfalls and edge cases

Knowledge Check

Question 1 of 4
Q1Single choice

Given f1=2.5f_1=2.5 GHz, CPI1=4\text{CPI}_1=4, f2=2f_2=2 GHz, and CPI2≈1\text{CPI}_2\approx 1 for a typical program, what is the speedup S=T1/T2S=T_1/T_2?

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