CPU Slowdown Due to DMA Cycle Stealing (16-bit Transfers)

We analyze a DMA subsystem using cycle stealing: while the DMA transfers data, it temporarily takes memory/bus access cycles away from the CPU, which reduces the CPU’s instruction throughput. To quantify the slowdown, we (1) convert the device’s character rate into the resulting DMA word rate, (2) determine how often the CPU loses cycles per DMA word (cycle stealing model), then (3) translate the lost cycles into an instruction-rate slowdown relative to the baseline CPU rate.

Key quantities in this problem:

• cycle stealing (assume 1 stolen CPU/bus cycle per transferred word for this standard word-at-a-time model)
• DMA transfer word rate (computed from character rate)
• instruction throughput (given as $10^6$ instr/s)
• slowdown factor

Step 1: Convert character transmission rate to DMA word transmission rate

The device transmits at 2400 characters per second. Each DMA transfer is a 16-bit word, and characters are typically 8-bit (1 byte) characters in such textbook DMA problems. Thus:

• 1 character = 8 bits = 1 byte
• 16-bit DMA word = 2 bytes = 2 characters

Therefore, the DMA word rate is:

So the DMA initiates 1200 word transfers per second.

If your course assumes a different character width (e.g., 16-bit characters), the conversion would change accordingly. Here, the “16-bit words assembled from characters” wording strongly implies 2 characters per word.

Step 2: Relate cycle stealing to CPU slowdown

With cycle stealing, the DMA steals CPU/bus cycles during each transfer. In the common simple performance model used in coursework:

• each transferred word costs the CPU 1 bus/memory cycle
• CPU instruction rate is reduced in proportion to the fraction of cycles stolen

If the CPU baseline completes instructions at $10^6$ instructions/s, then each missing CPU cycle reduces instruction completion proportionally. Under the standard assumption “1 stolen CPU cycle = 1 instruction time quantum” (i.e., instruction throughput scales linearly with available cycles), the slowdown fraction equals:

Here:

• $N_{\text{stolen}} = 1200$ stolen cycles/s (1 per word)
• $N_{\text{available}} = 10^6$ instruction cycles/s baseline (instruction throughput rate proxy)

So:

Step 3: Compute how much the CPU will be slowed down

If the CPU is slowed by a fraction $0.0012$, then the new effective CPU instruction rate is:

So the CPU slowdown is:

• Absolute drop:

• Relative slowdown:

Answer: The CPU will be slowed down by approximately $0.12\%$, dropping from $1.0\times 10^6$ to about $9.988\times 10^5$ instructions per second.