ROM Addressing for 4096 Bytes: Chip Count, Address Lines, and Common Addresses

To answer the questions, we rely on standard memory organization relationships:

• Address line count determines how many distinct locations a memory can address: $2^{A}$ locations for $A$ address lines.
• ROM organization relates capacity (in bytes) to addressable locations and word size.
• When multiple ROM chips are used to reach a larger total capacity, the chips typically share the same Address bus for the portion of the address that selects a location within each chip; the overall selection is done using Chip select.

We’ll assume the usual classroom-style premise for this type of problem: each ROM chip has a fixed capacity of 1024 bytes (i.e., $2^{10}$ bytes). Then producing 4096 bytes requires a straightforward scaling by powers of two.

Key formula set

1. Total addressable locations:

   $$\text{locations} = 2^{A}$$

   where $A$ is the number of address lines.

2. If each address corresponds to 1 byte (byte-addressable memory), then:

   $$\text{bytes} = 2^{A}$$

   This is the common assumption for problems phrased “bytes” with “address lines.”

3. If each ROM chip holds $C$ bytes, and you need $T$ bytes, then the number of chips is:

   $$N = \frac{T}{C}$$

   (assuming chips are used in a capacity-extension arrangement with decoding).

Final numeric answers

• ROM chips required: $4$
• Address lines required to access 4096 bytes: $12$
• Addresses common to all these chips (within-chip offsets): $1024$

We can also show how the 12 address lines split:

• Let the 12-bit CPU/overall address be $[A_{11}\dots A_0]$.
• Use the lower 10 bits $[A_9\dots A_0]$ to select a byte within each 1024-byte ROM chip.
• Use the upper 2 bits $[A_{11}\dots A_{10}]$ to decode which of the 4 chips is selected using chip-select lines.

keyword Within-chip offset is common across chips.