Designing a 32k × 32 RAM Using 128 × 8 Bit RAM Modules

To design a $32\text{k} \times 32$ bit RAM using smaller $128 \times 8$ bit RAM chips, we match two dimensions:

1. Depth (number of addressable words):
   $32\text{k}$ words must be formed by stacking chips in the “word-depth” direction (typically using chip-select / address decoding).

2. Width (bits per word):
   Each chip provides 8 bits per word, so we must combine chips to reach 32 bits per word.

We’ll compute the required chip count as:

• Number needed for width: $32/8$
• Number needed for depth: $32\text{k}/128$

Then total chips = (width chips) × (depth chips).

A helpful way to visualize the construction is:

Key keyword and [keyword]{def="Width: number of bits per stored word (e.g., 32 bits)} must align with the chip’s [keyword]{def="Memory word: one addressable unit of data (e.g., 32 bits)} and the chip organization’s keyword.

Interpretation of $128 \times 8$

A chip labeled $128 \times 8$ means:

• Depth = 128 addressable locations
• Word width = 8 bits per location

To build a larger RAM:

• Parallel chips increase the word width (8 → 32 via 4 chips)
• Multiple address segments increase the depth (128 → 32k via 256 segments)

Thus, total chips must scale in both dimensions:
$N = \left(\frac{32}{8}\right)\left(\frac{32\text{k}}{128}\right)=4 \times 256 = 1024$