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Explain I/O Transfer Techniques: Program-Controlled I/O, Interrupt-Driven I/O, and DMA

Explain I/O Transfer Techniques: Program-Controlled I/O, Interrupt-Driven I/O, and DMA

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Nov 3, 2026

I/O transfer techniques are strategies that determine how data moves between an I/O device and main memory, and how the CPU coordinates (or is kept out of the way of) that movement. Three canonical approaches are Program-Controlled I/O , Interrupt-Driven I/O , and DMA.

At a high level:

  • In Program-Controlled I/O the CPU repeatedly polls device status or otherwise controls each step.
  • In Interrupt-Driven I/O the device triggers an interrupt; the CPU then executes an ISR (interrupt service routine).
  • In DMA a DMA controller transfers blocks of data over the system bus, typically only interrupting the CPU at the start/end (and sometimes on errors).

These techniques trade off CPU overhead, latency, bus utilization, and implementation complexity. For a complete treatment, you typically map them to the roles of (i) device registers/FIFOs, (ii) an interrupt controller, and (iii) bus arbitration / DMA request-response signaling. 2

Footnotes

  1. Computer Organization / polling I/O overview (Program-controlled I/O concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Program-controlled_input%E2%80%93output) - Section describing program-controlled I/O. ↩

  2. Input–output: Interrupt-driven I/O (asynchronous interrupt handling) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Interrupt-driven_input%E2%80%93output) - Section describing interrupt-driven I/O behavior. ↩

Interrupt-Driven I/O and DMA (intro concepts)

Key learning targets

After studying this section, you should be able to:

  1. Describe the control flow and CPU involvement of Program-Controlled I/O.
  2. Explain how interrupts and ISRs enable Interrupt-Driven I/O.
  3. Explain DMA’s “offload” model and why it reduces CPU work and improves throughput using bus mastering and burst/bock transfers. 2

Footnotes

  1. Input–output: Direct memory access (DMA concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Direct_memory_access) - Section describing DMA and its role. ↩

  2. Direct memory access (DMA) overview: bus arbitration and transfer modes (https://en.wikipedia.org/wiki/Direct_memory_access) - Background on DMA controller operation and transfer mechanisms. ↩

1) Program-Controlled I/O

Program-Controlled I/O (also called polling or synchronous I/O) means the CPU controls the transfer by repeatedly reading device status registers (or otherwise waiting in software). The basic pattern is:

  • CPU issues a command by writing to a device control register (or I/O port / MMIO).
  • CPU waits until the device indicates readiness (data available / space available).
  • CPU then transfers data by reading/writing the data register.
  • Repeat for each data item or block.

Why it’s simple but inefficient

Polling consumes CPU cycles while the device is busy. If the device takes long relative to the CPU’s polling rate, the CPU either:

  • wastes time checking status, or
  • must block in a way that still requires some scheduling/overhead.

This approach can be acceptable when:

  • the device is fast,
  • traffic is light,
  • or simplicity is more important than maximizing throughput.

The conceptual distinction you should remember is: the CPU “actively drives” every step, rather than being passively notified or offloaded to a DMA controller.

Footnotes

  1. Computer Organization / polling I/O overview (Program-controlled I/O concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Program-controlled_input%E2%80%93output) - Section describing program-controlled I/O. ↩

Program-Controlled I/O (polling) transfer walkthrough

  1. 1
    Step 1

    CPU writes the appropriate command/control bits to the device (via I/O port or MMIO).

  2. 2
    Step 2

    CPU repeatedly reads a status register until a ready condition indicates data can be transferred (e.g., input data available or output buffer free).

  3. 3
    Step 3

    CPU reads or writes the device data register for the next unit of data.

  4. 4
    Step 4

    Repeat the poll+transfer loop for more units, or stop when the desired count is reached.

  5. 5
    Step 5

    CPU checks error/status bits and takes corrective actions (retry, abort, or report).

Optimization intuition for polling

If you must poll, reduce overhead by polling at a rate that matches expected device latency, and avoid per-byte polling by transferring larger units when device registers support it.

Polling can hurt real-time and throughput

Busy-wait polling can starve other work (especially on single-core systems) and increase effective latency due to CPU contention.

Terms to internalize (Program-Controlled I/O)

  • Polling
  • Status register
  • Control register
  • Device data register
  • MMIO

2) Interrupt-Driven I/O

Interrupt-Driven I/O reduces CPU waste by letting the device signal the CPU asynchronously. The CPU executes normal program code; when the device needs attention, it triggers an interrupt, causing the CPU to:

  1. Pause the current execution flow (save context).
  2. Jump to the interrupt service routine (ISR) associated with that device/interrupt source.
  3. Perform the minimal required register operations (e.g., move one unit or update buffers).
  4. Return from interrupt to resume previous execution.

This changes the control flow from “CPU waits by polling” to “CPU is interrupted only when work is ready.” Interrupt controllers arbitrate among pending interrupts and ensure correct delivery.

Typical use cases

  • Devices where events happen irregularly (e.g., network packets, keyboard input).
  • Devices where waiting for readiness should not block CPU execution.
  • Systems that require better CPU utilization than polling.

Where the CPU time goes

Interrupt-driven I/O shifts cost from “continuous polling” to:

  • interrupt frequency (how often interrupts occur),
  • ISR execution time (how much work you do per interrupt),
  • interrupt handling overhead (context save/restore, vectoring).

If every byte causes an interrupt, interrupt overhead can become significant; therefore designs often batch work per interrupt (e.g., using device FIFOs) so the ISR handles chunks rather than single bytes.

Footnotes

  1. Input–output: Interrupt-driven I/O (asynchronous interrupt handling) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Interrupt-driven_input%E2%80%93output) - Section describing interrupt-driven I/O behavior. ↩ ↩2

Interrupt-Driven I/O (conceptual) transfer walkthrough

  1. 1
    Step 1

    CPU configures the device interrupt enable bits and registers an ISR in the interrupt vector table.

  2. 2
    Step 2

    CPU issues the operation (e.g., “begin reception” or “begin transmission”) via control registers.

  3. 3
    Step 3

    CPU proceeds with other tasks; it does not poll continuously for readiness.

  4. 4
    Step 4

    When a condition occurs (data ready, transfer complete, error), the device triggers an interrupt.

  5. 5
    Step 5

    ISR acknowledges the interrupt, moves data between device registers and software buffers, and updates counters.

  6. 6
    Step 6

    ISR completes and the CPU returns to the interrupted code path.

ISR design principle

In many architectures, ISRs should do minimal essential work and defer longer processing to threads/tasklets to keep interrupt latency low.

Terms to internalize (Interrupt-Driven I/O)

  • Interrupt
  • ISR
  • Interrupt vector
  • Interrupt latency
  • FIFO

3) DMA (Direct Memory Access)

DMA exists to overcome a core inefficiency: program- or interrupt-driven I/O often requires the CPU to move each data unit between device registers and memory. DMA offloads bulk transfers by having a dedicated controller move data directly between a device and main memory.

DMA’s core idea

  • The CPU programs the DMA controller with: source address (or device), destination address (or memory), transfer length, and transfer mode.
  • The DMA controller becomes (at least temporarily) the bus master and performs transfers over the system interconnect.
  • The DMA controller signals completion to the CPU, usually via an interrupt. 2

Bus and cycle behavior (conceptual)

DMA must coexist with CPU memory accesses. Many systems use techniques such as:

  • cycle stealing (DMA takes some bus cycles between CPU accesses),
  • burst transfers (DMA transfers a contiguous block in a burst),
  • arbitration (bus grants DMA controller time according to priority).

These mechanisms reduce CPU involvement while still maintaining correct system operation.

Why DMA improves throughput

DMA is especially beneficial for:

  • high-bandwidth devices (storage, network),
  • large transfers (buffers, frames, blocks),
  • systems where CPU time is scarce.

The CPU overhead becomes closer to “setup + completion handling” rather than “per-byte copying.” 2

Footnotes

  1. Input–output: Direct memory access (DMA concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Direct_memory_access) - Section describing DMA and its role. ↩ ↩2

  2. Direct memory access (DMA) overview: bus arbitration and transfer modes (https://en.wikipedia.org/wiki/Direct_memory_access) - Background on DMA controller operation and transfer mechanisms. ↩ ↩2 ↩3

DMA transfer lifecycle (conceptual)

  1. 1
    Step 1

    CPU writes DMA parameters: source/destination, length, and control flags to DMA registers.

  2. 2
    Step 2

    CPU sets a start bit; DMA begins requesting data on the relevant device interface.

  3. 3
    Step 3

    DMA arbitrates for bus access and transfers data between device and RAM (often in bursts).

  4. 4
    Step 4

    When length reaches zero (or an error occurs), DMA signals completion (usually via interrupt).

  5. 5
    Step 5

    CPU ISR (or driver callback) verifies status, updates software buffers/metadata, and schedules next transfer if needed.

DMA correctness constraints

DMA requires careful handling of cache coherency, buffer ownership, and alignment; otherwise data corruption or stale reads can occur.

Terms to internalize (DMA)

  • DMA controller
  • Bus master
  • Cycle stealing
  • Burst transfer
  • Cache coherency

Direct comparison (CPU overhead vs throughput)

The following table summarizes the qualitative differences among the three techniques.

TechniqueCPU involvement during data movementTypical triggerBest suited for
Program-Controlled I/OHigh (CPU checks readiness + copies data)CPU polling loopSimple/low-rate devices
Interrupt-Driven I/OMedium (CPU copies data in ISR)Device interruptIrregular events and moderate rates
DMALow (DMA controller copies bulk data)DMA completion (interrupt)High bandwidth and large transfers

These distinctions align with standard architecture treatments: polling makes CPU busy, interrupts reduce busy-waiting, and DMA offloads bulk transfer work with bus arbitration. 4

Footnotes

  1. Computer Organization / polling I/O overview (Program-controlled I/O concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Program-controlled_input%E2%80%93output) - Section describing program-controlled I/O. ↩

  2. Input–output: Interrupt-driven I/O (asynchronous interrupt handling) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Interrupt-driven_input%E2%80%93output) - Section describing interrupt-driven I/O behavior. ↩

  3. Input–output: Direct memory access (DMA concept) (https://en.wikipedia.org/wiki/Input%E2%80%93output#Direct_memory_access) - Section describing DMA and its role. ↩

  4. Direct memory access (DMA) overview: bus arbitration and transfer modes (https://en.wikipedia.org/wiki/Direct_memory_access) - Background on DMA controller operation and transfer mechanisms. ↩

Relative CPU involvement during transfer (qualitative)

Higher bar = more CPU work involved in moving data

How the CPU interacts during each technique

CPU polls

Program-Controlled I/O

CPU repeatedly checks readiness and copies data registers → memory."

CPU sleeps until interrupt

Interrupt-Driven I/O

Device interrupts; ISR copies data and updates buffers."

DMA performs bulk copy

DMA

CPU configures DMA; DMA copies and interrupts only on completion/errors."

Common edge cases and practical notes

I/O Transfer Techniques — Quick Recall

1 / 5
Question · Term

Program-Controlled I/O

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Answer · Definition

CPU explicitly checks device status and copies data via registers (polling/synchronous control).

Knowledge Check

Question 1 of 4
Q1Single choice

In program-controlled (polling) I/O, the CPU primarily does which action while waiting for the device?

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