Direct Memory Access (DMA): Definition and Peripheral Data Transfer
Direct Memory Access (DMA) is a mechanism that moves data between a computer’s peripherals (e.g., disk, network, audio codecs) and main memory (RAM) while largely avoiding CPU involvement in the actual byte transfer. Instead of the CPU performing repeated “read from device → write to memory” operations, DMA hardware can perform the bus transactions needed to move blocks of data, while the CPU is free to run other code and only handles setup, configuration, and completion events.
At a high level, a DMA-capable system includes a DMA controller and one or more DMA channels (or request lines). Peripherals signal DMA requests when they need service (e.g., receive a packet, transmit an audio buffer). The DMA controller then performs [read/write memory bus cycles]{def="Low-level memory operations DMA uses to move data} using the system interconnect and writes the transferred data into RAM (or reads from RAM into the peripheral).
DMA is widely used for throughput-critical transfers because it reduces CPU overhead and can increase effective data rate by using optimized transfer patterns and minimizing interrupt frequency. The CPU typically configures the DMA transfer descriptors (source, destination, size, increment rules, and mode), enables the channel, and then responds to interrupts (e.g., “transfer complete” or “half complete”).
DMA (Direct Memory Access) Explained
Key DMA terms you’ll see in datasheets and programming guides
- DMA request: the peripheral’s request to move data
- DMA transfer: controlled movement of a block (or streaming segment)
- Transfer descriptor: what the DMA engine uses to execute the transfer
- Interrupt on completion: used to synchronize software with hardware
Typical DMA Usage Flow (Peripheral → Memory or Memory → Peripheral)
Setup
1) Software configuresDriver programs channel, source/destination addresses, transfer size, and mode."
DMA starts
2) Peripheral raises requestPeripheral asserts a request when it has data to send (or space to receive)."
Data movement
3) DMA performs bus transactionsDMA controller reads/writes memory and transfers to/from the peripheral."
Streaming/blocks
4) Optional milestonesSome systems use half-buffer/periodic interrupts or scatter-gather lists."
Interrupt + post-processing
5) DMA signals completionCPU handles completion interrupt and updates software state (e.g., buffer indices)."
How DMA transfers data from peripherals (conceptual mechanism)
Consider two common scenarios:
-
Peripheral → Memory (e.g., network receive, ADC sampling into RAM)
- The peripheral produces data (or indicates availability).
- It asserts a DMA request.
- The DMA controller transfers incoming data into a target memory buffer.
- When the configured number of bytes/words are moved, DMA signals completion.
-
Memory → Peripheral (e.g., network transmit, DAC output)
- The peripheral asserts a DMA request when it is ready to consume data.
- DMA reads data from a source buffer in RAM.
- DMA writes that data into the peripheral’s data register or FIFO.
- DMA signals completion after the configured transfer length.
The CPU is not required to copy each individual datum; it only initiates and reacts.
Peripheral-to-Memory DMA Transfer (Receive Path) — Step-by-step
- 1Step 1
Software selects a DMA channel and binds it to the peripheral’s RX request line.
- 2Step 2
Configure peripheral source (e.g., data register/FIFO address), memory destination (buffer address), transfer length, and whether the memory address should increment.
- 3Step 3
Choose mode such as single-shot (one block) vs. continuous/streaming; configure packing/alignment if required by the controller.
- 4Step 4
Start the peripheral logic (e.g., enable RX) and enable DMA so it can respond to requests.
- 5Step 5
As the peripheral FIFO becomes non-empty, it signals DMA requests at a rate determined by hardware flow-control.
- 6Step 6
For each request (or burst), DMA transfers a unit (byte/word) or a burst of units from the peripheral into RAM.
- 7Step 7
When the programmed length is reached, DMA raises an interrupt (e.g., completion or error).
- 8Step 8
CPU updates buffer pointers/indices, wakes waiting threads, and schedules the next transfer if using cyclic buffers.
Bus mastering and arbitration (why DMA works without the CPU moving bytes)
DMA hardware must still move data across the system interconnect. In many designs, the DMA controller becomes a bus master for the duration of the transfer, or uses specialized pathways (e.g., DMA engines tied into the memory system). Because multiple masters may compete for memory access, the DMA controller typically:
- Arbitrates bus access,
- Performs burst transfers,
- Handles alignment and word sizing.
This coordination is what allows high throughput while avoiding CPU involvement in each individual move.
[CalloutBlock] warning (DMA impact): Even though DMA reduces CPU copying overhead, DMA still consumes memory bandwidth and bus time. Excessive or poorly configured DMA can increase latency for CPU loads/stores.