Direct Memory Access (DMA): Concept, Operation, and Required Circuitry
Direct Memory Access (DMA) is a technique where a dedicated DMA controller takes over control of a system memory bus to move blocks of data between an I/O device and main memory. In a DMA transfer, the CPU typically initializes the transfer by programming DMA controller registers, after which the DMA hardware performs the repeated read/write cycles autonomously, only signaling the CPU when needed (e.g., completion or error). This reduces CPU load and improves throughput for high-bandwidth peripherals.2
Key idea: “CPU is free while hardware transfers”
Instead of the CPU executing a loop like “read device → write memory” for every element, DMA uses hardware to:
- arbitrate for bus access (become a bus master),
- generate memory addresses (via an internal address counter),
- stream data transfers over the bus using DMA control logic,
- track transfer count and completion,
- optionally coordinate with device handshaking via request/acknowledge signals.2
Why DMA matters
DMA is especially useful when transfers are large (e.g., disk/network buffers). Many system designs use DMA to avoid wasting CPU cycles on per-transfer software overhead and to better utilize bus bandwidth.2
Footnotes
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Direct memory access (DMA) — Wikipedia (overview of DMA purpose and concept) https://en.wikipedia.org/wiki/Direct_memory_access ↩ ↩2
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Direct memory access — IBM (conceptual description of DMA offloading CPU transfers) https://www.ibm.com/docs/en/i/7.4?topic=memory-direct-access ↩ ↩2 ↩3
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DMA modes and bus mastering concepts — Wikipedia (DMA arbitration and cycle stealing/burst-related ideas) https://en.wikipedia.org/wiki/Direct_memory_access ↩
DMA (Direct Memory Access) Overview
DMA circuitry: functional blocks you need
A practical DMA implementation is best understood as a set of cooperating blocks. The essential circuitry generally includes:
- Bus master / arbitration interface to obtain bus access from the interconnect/arbiter.
- Address generator (address counter).
- Transfer counter + control/status registers.
- Data path interface (read/write engine).
- Device interface & handshaking.
- Interrupt controller interface.
The following block diagram shows these elements in a typical DMA-based system.
Block diagram of typical DMA circuitry for direct memory access
Interpretation (how signals flow):
- CPU programs DMA controller registers: start address, transfer length, direction (device→memory or memory→device), and mode.2
- DMA control logic requests the bus and waits for arbiter grant to become bus master.
- Address generator produces sequential memory addresses for each beat/word.
- Transfer counter decrements per transfer and halts DMA when terminal count is reached.
- Read/write engine performs actual memory bus cycles while routing data to/from the device interface.
- Device handshake ensures DMA moves data only when the peripheral is ready (request/acknowledge or similar readiness signals).
- Interrupt interface informs the CPU on completion (and sometimes intermediate events).
Footnotes
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Direct memory access — IBM (conceptual description of DMA offloading CPU transfers) https://www.ibm.com/docs/en/i/7.4?topic=memory-direct-access ↩
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DMA controller programming concepts (address/count/mode initialization) — Intel (DMA controller background and usage patterns) https://www.intel.com/content/www/us/en/developer/topic-technology/embedded/dma.html ↩
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DMA modes and bus mastering concepts — Wikipedia (DMA arbitration and cycle stealing/burst-related ideas) https://en.wikipedia.org/wiki/Direct_memory_access ↩
End-to-end DMA transfer workflow (device ↔ memory)
- 1Step 1
CPU writes start address, transfer count, direction, and mode into the DMA controller’s control/status registers.
- 2Step 2
DMA asserts a bus request to the system arbiter and waits for a grant so it can drive address/control lines.
- 3Step 3
DMA uses an internal address counter to output each successive memory address and issues appropriate read/write bus control signals.
- 4Step 4
For each beat, DMA synchronizes with the peripheral using handshake signals, then transfers one unit of data over the data path.
- 5Step 5
The transfer counter decrements each unit; when it reaches terminal count, DMA stops bus activity.
- 6Step 6
DMA asserts an interrupt/status flag for completion (and may provide error details).
DMA transfer modes (high-level)
DMA implementations commonly support multiple operating modes to match bus and device behavior, such as:
- Cycle stealing (DMA steals cycles from CPU during CPU execution).
- Burst mode (higher efficiency on buses that support burst transfers).
- Scatter-gather (common in modern controllers for non-contiguous buffers).2
Footnotes
-
DMA modes and bus mastering concepts — Wikipedia (DMA arbitration and cycle stealing/burst-related ideas) https://en.wikipedia.org/wiki/Direct_memory_access ↩
-
Scatter-gather DMA — Wikipedia (non-contiguous buffer lists) https://en.wikipedia.org/wiki/Scatter-gather I/O ↩
Conceptual comparison of DMA modes (efficiency vs. bus occupation)
Qualitative comparison commonly used to reason about trade-offs.
Pro Tip
When drawing a DMA diagram, always include: bus arbitration/grant, memory address generation, transfer-count termination, and the device handshake—those are the minimum ‘physics’ blocks needed for correctness.
Common misconception
DMA does not mean the CPU is completely uninvolved: the CPU usually programs DMA controller registers and may be interrupted for completion/error. The CPU just avoids per-transfer data movement work.
How DMA interacts with the CPU and the bus
Knowledge Check
In a DMA system, what is the main role of the DMA controller?