Addressing Modes in a CPU: Concepts and Worked Examples

In a CPU, an instruction often needs an operand (a value to use or a memory location to read/write). An addressing mode specifies how the CPU interprets the operand field in the instruction—either as an immediate value or as a way to compute an effective address (EA). This matters for both performance (how quickly operands are found) and correctness (which exact memory location is referenced).

At a high level, addressing modes fall into two categories:

• Register/immediate-like modes: the operand is in the instruction itself or in a CPU register.
• Memory-reference modes: the operand is found by computing an address using a base register, index register, displacement/offset, scaling, or indirection.

A useful mental model is:

• The instruction contains some bits naming registers and/or constants.
• The CPU applies the addressing-mode rule to determine either:
  • the operand value directly, or
  • the effective address, then reads/writes memory at that EA.

Key terms you’ll see repeatedly:

• effective address
• displacement/offset
• base register
• index register
• indirection

Common addressing modes (with what they mean)

Different CPU ISAs describe addressing modes slightly differently, but the underlying patterns are consistent.

1. Immediate addressing

   • The operand value is embedded in the instruction itself.
   • Example idea: ADD R1, #5 means “add 5 to R1”.

2. Register addressing

   • The operand is in a named register.
   • Example idea: ADD R1, R2.

3. Direct (absolute) memory addressing

   • The instruction contains (or refers to) a full memory address constant.
   • Example idea: LOAD R1, [0x1000].

4. Register indirect

   • A register contains the memory address (a pointer).
   • Example idea: LOAD R1, [R3] where R3 points to the memory location.

5. Base + displacement (base-relative)

   • Effective address is formed as EA = Base + displacement.
   • Example idea: LOAD R1, [Rbp + 8].

6. Index (indexed) addressing

   • Effective address includes an index register (often with a scale).
   • Example idea: LOAD R1, [Rbase + Rindex] or EA = base + index*scale.

7. Base + index + displacement

   • Common in array access and data structures.
   • Often: EA = base + index*scale + displacement.

8. Scaled indexed addressing

   • A scale factor accounts for element size (e.g., 4 bytes for 32-bit ints).
   • Example idea: EA = base + index*4.

Note: Exact syntax differs by ISA (e.g., x86 uses “effective address” with forms like base+index*scale+disp; ARM uses variants for load/store and register+offset forms). The conceptual structures above still apply.

Visual comparison of the EA rules

The table below focuses on how the effective address $EA$ is computed (or whether an EA is needed at all).

Worked “one loop” example: array element access via different modes

Consider accessing A[i] where A is an array of 4-byte integers.

Assume:

• $R_{base}$ holds the base address of A
• $R_i$ holds the integer index $i$
• Each element is 4 bytes

Then the memory read uses:

• Scaled indexed addressing: $EA = R_{base} + R_i \cdot 4$

So a conceptual LOAD Rval, [Rbase + R_i*4] reads $M[EA]$, i.e., the value at A[i].

In contrast:

• Immediate addressing would not make sense for array indexing because $i$ varies per iteration, and immediate addressing fixes the operand value at assembly time.
• Register indirect could be used if you first compute a pointer to A[i] (e.g., compute $R_{ptr}=R_{base}+R_i*4$ somewhere, then LOAD Rval, [Rptr]).

This is why modern compilers and ISAs emphasize addressing-mode arithmetic: it reduces extra instructions by folding address calculation into the load/store itself.