Design a 3-Bit Flash ADC and Explain Its Working with an Example | AI Research

Design a 3-Bit Flash ADC and Explain Its Working (with an Example)

Verified Sources

Nov 4, 2026

A flash ADC (a “parallel” ADC) determines the digital output by comparing the input voltage against a set of reference thresholds. For an $N$ -bit flash ADC, you typically use $2^N-1$ comparators to generate a thermometer code that is then converted to the binary output via an encoding stage. The quantization produces $2^N$ output codes spanning the designed input range, usually $[0, V_\text{ref}]$ or $[V_\text{min}, V_\text{max}]$ .

Below, we design a complete 3-bit flash ADC (so $2^3-1=7$ comparators), derive the thresholds, show thermometer-code generation, and work through a numeric example step-by-step.

Mermaid overview of the full signal chain:

Key learning terms: flash ADC, LSB , thermometer code, comparator threshold.

Step-by-Step: Design a 3-Bit Flash ADC

1
Step 1
Assume a unipolar input range $[0, V_\text{ref}]$ . Then the 3-bit LSB size is $\text{LSB}=V_\text{ref}/2^3=V_\text{ref}/8$ .
2
Step 2
A 3-bit flash ADC uses $2^3-1=7$ thresholds at multiples of LSB: $T_k=k\cdot\text{LSB}=k\cdot V_\text{ref}/8$ for $k=1,2,\dots,7$ .
3
Step 3
Create comparator $k$ that outputs 1 when $V_\text{in}\ge T_k$ (and 0 otherwise). Comparator outputs form a 7-bit thermometer code where bits become 1 progressively as $V_\text{in}$ rises.
4
Step 4
For a given $V_\text{in}$ , determine the largest $k$ such that $V_\text{in}\ge T_k$ . Then the thermometer code has $k$ ones followed by $(7-k)$ zeros (assuming ordering from lowest to highest threshold).
5
Step 5
Let the number of asserted thermometer bits be $k$ . The 3-bit output code is typically $D=k$ (i.e., code 0 corresponds to $V_\text{in}<T_1$ , code 7 corresponds to $V_\text{in}\ge T_7$ ).
6
Step 6
The ideal quantization bins are: code $m$ for $m\in\{0,1,\dots,7\}$ when $m\cdot\text{LSB}\le V_\text{in}<(m+1)\cdot\text{LSB}$ for $m=0\dots6$ , and code 7 when $V_\text{in}\ge 7\cdot\text{LSB}$ .

Threshold table and ideal transfer for a 3-bit flash ADC

Let $\\text{LSB}=V_\\text{ref}/8$ and thresholds $T_k=k\\cdot\\text{LSB}$ for $k=1..7$ . Comparator $k$ asserts when $V_\\text{in}\\ge T_k$ .

Comparator outputs vs. input region

3-bit code $m$	Input range (ideal)	Highest satisfied threshold $k$	Thermometer code (7 bits)
0	$0\\le V_\\text{in}<T_1$	$k=0$	0000000
1	$T_1\\le V_\\text{in}<T_2$	$k=1$	1000000
2	$T_2\\le V_\\text{in}<T_3$	$k=2$	1100000
3	$T_3\\le V_\\text{in}<T_4$	$k=3$	1110000
4	$T_4\\le V_\\text{in}<T_5$	$k=4$	1111000
5	$T_5\\le V_\\text{in}<T_6$	$k=5$	1111100
6	$T_6\\le V_\\text{in}<T_7$	$k=6$	1111110
7	$V_\\text{in}\\ge T_7$	$k=7$	1111111

Notes:

The thermometer code is ordered from lowest threshold to highest (so “earlier” comparators correspond to lower $T_k$ ).
The encoder can be implemented as a logic network that maps the thermometer pattern to the 3-bit value $m$ . In an ideal monotonic case, counting the number of 1s is equivalent to $m$ .

Key learning terms: quantization, encoder, comparator bank.

Tip: Unipolar 3-bit flash ADC thresholding

With $[0,V_\text{ref}]$ and $N=3$ , the thresholds are evenly spaced at $V_\text{ref}/8, 2V_\text{ref}/8,\dots,7V_\text{ref}/8$ . Using a resistor ladder is the standard way to generate these equally spaced reference levels.

Example: Work through a 3-bit flash ADC conversion

Assume:

$V_\\text{ref}=1.6\\,\\text{V}$
Therefore $\\text{LSB}=V_\\text{ref}/8=1.6/8=0.2\\,\\text{V}$
Thresholds:
- $T_1=0.2$ , $T_2=0.4$ , $T_3=0.6$ , $T_4=0.8$ , $T_5=1.0$ , $T_6=1.2$ , $T_7=1.4$ (in volts)
Choose input: $V_\\text{in}=0.74\\,\\text{V}$

Step 1: Determine which thresholds are met

Check $V_\\text{in}$ against each $T_k$ :

$0.74 \\ge 0.2$ (C1 = 1)
$0.74 \\ge 0.4$ (C2 = 1)
$0.74 \\ge 0.6$ (C3 = 1)
$0.74 \\ge 0.8$ (C4 = 0)
Then higher thresholds (1.0, 1.2, 1.4) are also not met (C5–C7 = 0)

So the 7-bit thermometer code is:

C1..C7 = 1110000 (i.e., 3 ones then 4 zeros)

Step 2: Convert thermometer count to 3-bit output

Number of 1s is $k=3$ , so the 3-bit binary code is:

$D=m=k=3$
In binary, $3\\rightarrow \\mathbf{011}$ (3-bit)

Step 3: Verify using the ideal quantization bins

For code $m=3$ the input range is:

$3\\cdot\\text{LSB} \\le V_\\text{in} < 4\\cdot\\text{LSB}$
$0.6 \\le 0.74 < 0.8$ ✔️

So output is consistent: Dout = 011.

Key learning terms: quantization step, decision threshold, thermometer-to-binary encoding.

Warning: Non-ideal comparators and missing codes

Real flash ADCs can suffer from comparator offset, gain error, and metastability, which may break monotonicity (e.g., “bubble” errors) and cause missing/extra codes. Practical designs often calibrate or add redundancy/thermometer correction logic.

From Resistor Ladder to 3-Bit Code (Lifecycle View)

Resistor-ladder thresholds

1. Reference generation

Generate 7 evenly spaced levels from $V_\text{ref}$ using a resistor string."

Comparator bank

2. Parallel decision

Each comparator decides if $V_\text{in}\ge T_k$ ."

Thermometer -> binary

3. Digital logic

Encode monotonic comparator outputs into $D_2D_1D_0$ ."

Synchronized digital result

4. Output

Ideal 3-bit code bins across 0 to Vref

Each bar width is one LSB. A value falls into exactly one bin (ideal case).

Common design/explanation questions

Flash ADC concept and comparator bank intuition

Knowledge Check

Question 1 of 4

Q1Single choice

A 3-bit ideal flash ADC uses how many comparators?

Explore Related Topics

Understanding Digital Counters: Principles, Types, and Applications

Digital counters are sequential circuits built from cascaded flip‑flops that count input events, with a maximum modulus of 2ᴺ for N stages, and are classified as asynchronous (ripple) or synchronous based on clock distribution.

Asynchronous counters cascade flip‑flop clocks, causing cumulative propagation delay and limiting maximum frequency.
Synchronous counters receive the clock simultaneously, using combinational logic to eliminate ripple delay and support higher speeds.
Designing a synchronous Mod‑6 counter involves defining the state sequence, creating excitation tables, simplifying with Karnaugh maps, and wiring JK flip‑flops with derived logic.
Ring counters yield N states; Johnson counters double this to 2N states.
Prevent glitches and lock‑out by using Gray‑code sequencing, output strobes, and ensuring unused states redirect to the main count sequence.

Design and Logic of a Microprogram Sequence

Ladder DAC Working: R–2R Operation and Signal Flow

Browse all research articles