Ladder DAC Working: R–2R Operation and Signal Flow

A DAC (digital-to-analog converter) produces an analog output from a digital input code. The most common “ladder DAC” structures implement weighted addition using a network of resistors arranged like a ladder.

Two closely related “ladder” families are widely discussed:

1. R–2R ladder DAC: Uses only two resistor values ($R$ and $2R$) to create weights of $1/2, 1/4, 1/8, \dots$ without using fully binary-weighted resistor values.
2. Resistor-string ladder DAC: Uses a series string of resistors and taps, often interpreted as proportional division along the string.

In practice, most introductory and many engineering discussions of “ladder DAC” refer to the R–2R ladder DAC, because it is area- and tolerance-friendly (only $R$ and $2R$ values needed). The working principle is that each bit connects (via a switch) either to a reference level or to ground, and the resistor ladder ensures the resulting currents/voltages sum with binary weights.

Key terms

• R–2R ladder
• MSB/LSB
• Switching node
• Reference voltage

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Functional diagram: how a ladder DAC “routes” bits

Below is a conceptual block diagram showing the major components: digital input bits, bit switches, the resistor ladder, and an output summing/termination stage (often an op-amp in current-output DAC configurations).

Each bit $B_k$ connects a corresponding ladder node to either $V_{\text{ref}}$ or GND. The ladder network then translates those switch connections into a weighted contribution to the final analog output.

R–2R ladder network: signal-flow and weighting

An R–2R ladder DAC is typically drawn as an alternating series of $R$ and $2R$ resistors. Conceptually, it behaves like a “current-splitting” network where each stage contributes a fraction of the full-scale.

For an $N$-bit DAC, the ideal output can be expressed (for the common current-to-voltage configuration) as:

$V_{\text{out}} = V_{\text{ref}} \cdot \frac{D}{2^N}$

where $D$ is the unsigned integer value of the digital code: $D=\sum_{k=0}^{N-1} B_k \cdot 2^k$

Equivalently, using MSB-first weighting: $\text{Normalized output} = \sum_{k=0}^{N-1} B_{k}\cdot 2^{-(N-k)}$

The ladder ensures each bit’s contribution scales by a factor of $1/2$ relative to the next higher bit.

Diagram: stage-by-stage interpretation (binary-weighted contributions)

Consider a simplified 4-bit conceptual R–2R ladder. Each bit controls a switch at a “tap” that connects to $V_{\text{ref}}$ (logic 1) or to GND (logic 0).

Intuition: When $B_3=1$, the MSB stage causes the largest incremental contribution; when only $B_0=1$, the output changes by the smallest increment ($1/2^N$ of full-scale).

Why the R–2R ladder achieves binary weights with only two resistor values

A common design goal is to avoid using resistor values proportional to $2^k$ (which would be difficult to realize precisely with real resistor tolerances). The R–2R ladder uses symmetry and recursion:

• The ladder is designed so that the equivalent resistance “seen” into the next stage becomes a predictable function of $R$ and $2R$.
• When combined with the fact that each bit switch either applies $V_{\text{ref}}$ or 0 V, the resulting incremental output contribution naturally forms a geometric series with ratio $1/2$.

This is why R–2R DACs are favored in many practical designs: they are compact and tolerant-friendly (only $R$ and $2R$ are required).