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Control Sequence for Three-Bus Structure: ADD R4, R5, R6 (Micro-operations)

Control Sequence for Three-Bus Structure: ADD R4, R5, R6 (Micro-operations)

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Nov 3, 2026

In a three-bus CPU, the register file has independent read ports for the two ALU operands (typically driven onto buses A and B) and a separate write path from the ALU result onto bus C into the destination register. The ALU operation (here, addition) is selected by ALU control lines, and the result is written into the specified destination register in the execute phase. This avoids extra intermediate registers needed in single-bus designs and shortens the control sequence for multi-register operations such as R6←R4+R5R6 \leftarrow R4 + R5.2

Key components (used in the control steps)

  • keyword: Signal that selects the ALU function (e.g., Add).
  • keyword: Atomic step like “Ri←R_i \leftarrow bus” performed under control signals.
  • keyword: Datapath using separate buses for ALU inputs and ALU result write-back.
  • keyword: Step ensuring memory read/write has completed before using MDR.

Footnotes

  1. CST202 - Computer Organization and Architecture Module: 1 - Describes three-bus datapath and shows control sequence example including simultaneous ALU operand use and result write-back. ↩ ↩2

  2. IAT-III Question Paper with Solution (18CS34) - Three-bus control sequence for ADD R4, R5, R6 - Provides explicit three-bus control sequence for the requested instruction. ↩

  3. Krishnagudi CO Notes - Unit 7: Basic Processing Unit (control sequence for Add R4,R5,R6) - Lists the control steps including WMFC and the register/output operations for the add. ↩

Three-bus structure and control sequence for ADD R4, R5, R6

Assumed instruction and notation

We implement the instruction semantics:

  • Instruction: ADD R4, R5, R6
  • Meaning: R6←R4+R5R6 \leftarrow R4 + R5

We write a sequence of control steps (micro-operations) in the standard instruction-cycle style:

  1. Fetch instruction
  2. Decode / operand prep (often included implicitly)
  3. Execute (read R4 & R5 to ALU, add, write into R6)

Control steps below include the conventional memory handshaking step WMFC used when reading main memory into MDR.

Footnotes

  1. Krishnagudi CO Notes - Unit 7: Basic Processing Unit (control sequence for Add R4,R5,R6) - Lists the control steps including WMFC and the register/output operations for the add. ↩

Visual intuition (data flow in execute stage)

  • Buses A and B carry the two register operands to the ALU.
  • Bus C carries the ALU output to the destination register.

This matches the described three-bus behavior: two register outputs go to ALU inputs and the ALU result goes to the third register via the result bus.2

Footnotes

  1. CST202 - Computer Organization and Architecture Module: 1 - Describes three-bus datapath and shows control sequence example including simultaneous ALU operand use and result write-back. ↩

  2. IAT-III Question Paper with Solution (18CS34) - Three-bus control sequence for ADD R4, R5, R6 - Provides explicit three-bus control sequence for the requested instruction. ↩

Sequence of control steps for `ADD R4, R5, R6` in a three-bus CPU

  1. 1
    Step 1

    Set PCout, R=B, MARin, Read, IncPC (start instruction fetch from memory using PC).

  2. 2
    Step 2

    Execute WMFC to ensure the memory read completes.

  3. 3
    Step 3

    Set MDRout, R=B, IRin to load the fetched instruction into the IR.

  4. 4
    Step 4

    Enable R4outA and R5outB, set SelectA so the ALU input A comes from bus A, set Add in the ALU, and then load the ALU result into R6 using R6in.

  5. 5
    Step 5

    Instruction execution completes after the result is written to R6.

What each execute step achieves (operand placement + ALU action)

  • R4outA: drives [R4][R4] onto ALU input path A (bus A).
  • R5outB: drives [R5][R5] onto ALU input path B (bus B).
  • Add: configures the ALU to compute A+BA + B.
  • R6in: writes the ALU sum into register R6R6.

This execute-stage pattern is the essence of three-bus control: the two source registers can be presented to the ALU simultaneously, and the result is written back independently to the destination register.2

Footnotes

  1. CST202 - Computer Organization and Architecture Module: 1 - Describes three-bus datapath and shows control sequence example including simultaneous ALU operand use and result write-back. ↩

  2. IAT-III Question Paper with Solution (18CS34) - Three-bus control sequence for ADD R4, R5, R6 - Provides explicit three-bus control sequence for the requested instruction. ↩

Mnemonic sanity check

If your control sequence has two separate lines like R4outA and R5outB before Add, you’re correctly using the three-bus feature (simultaneous ALU inputs). The last write should target R6.

Don’t skip WMFC for main-memory reads

"The fetched instruction must be valid in MDR before transferring MDRout into IRin. Many exam solutions explicitly include WMFC between Read and MDRout."

Footnotes

  1. Krishnagudi CO Notes - Unit 7: Basic Processing Unit (control sequence for Add R4,R5,R6) - Lists the control steps including WMFC and the register/output operations for the add. ↩

Control-step grouping (high-level)

How the sequence divides across instruction-cycle phases

Instruction cycle timeline for ADD R4, R5, R6

Fetch

t1

PCout -> MARin, Read, IncPC"

Wait

t2

WMFC ensures memory read completes"

IR Load

t3

MDRout -> IRin"

Execute (three-bus add)

t4

R4outA & R5outB, ALU=Add, result -> R6in"

Common variations you may see in solutions

Knowledge Check

Question 1 of 3
Q1Single choice

In the three-bus datapath execute stage for ADD R4, R5, R6, the ALU should receive its two operands from which buses?

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