Content-Addressable Memory (CAM): Organization and Operation

Content-Addressable Memory (CAM) is a memory architecture in which lookup is performed by content, not by address: the hardware compares an input “search key” against stored “words” and returns the matching location(s) (often as a match-line–driven one-hot vector). This contrasts with conventional RAM, where data is retrieved using an address. CAMs are widely used in fast association tasks such as cache tag lookup, TLB lookups, routing/forwarding tables, and network address filtering.

A practical CAM organization is typically built from:

• Match line logic across each stored entry.
• Comparator replicated per cell/entry (often implemented via cell-level match logic).
• Priority encoder when multiple entries can match.
• Valid bit for ignoring unused entries.
• One-hot output or encoded index output.

The core operation is: write/program stored patterns into entries, then for a read/search, broadcast the key to all entries in parallel, compute match conditions in the same cycle (or over a small pipeline), and finally select the match result (e.g., highest-priority match).

Key learning terms: CAM Match line Priority encoder Valid bit One-hot output.

Important performance note: CAM search is “parallel by design” across entries, but CAMs often consume more area and power than SRAM for the same capacity because of the associative comparison hardware replicated throughout the array.

Organization of a CAM

A CAM can be viewed as an array of associative cells (or associative rows/entries), supported by peripheral circuits for writing and for producing match outputs.

1) Associative cell / row structure

Most CAM designs use cell-level comparison that converts the stored bit(s) and the incoming key bit(s) into match contributions that are combined across the word width:

• Each CAM row corresponds to one stored entry.
• Within a row, per-bit compare logic determines whether that row’s pattern matches the incoming key across all bit positions.
• The result of the row comparison is typically a match line signal.

At the row level, a match usually behaves like a word-wide AND of all per-bit equality conditions:

• For bit $j$, the cell decides whether stored bit $S_j$ equals key bit $K_j$ (or matches according to a more general scheme such as ternary CAM).
• Across the row, all equality results must be true for a global match.

2) CAM array partitions and banked operation

Large CAMs are commonly partitioned into banks to manage:

• wiring length (match-line delay),
• power during parallel evaluations,
• output fan-in and encoder complexity,
• timing closure at high clock rates.

3) Per-entry control: valid bits and masks

Real CAMs frequently include:

• Valid bit per row, so invalid/empty entries do not generate false matches.
• In some designs, partial comparators/masks allow selective matching (e.g., “don’t care” fields). A common extension is ternary CAM where each bit can be “0”, “1”, or “X” (don’t care).

4) Match output formation: one-hot vs encoded index

CAMs support different readout interfaces:

• One-hot match vector: multiple matching entries can be represented simultaneously as asserted bits.
• Priority/leading-match output: when multiple matches exist, a priority encoder selects the “first” match according to row ordering or stored priority.

These blocks often run combinationally or over a small pipeline stage.

Key learning terms: Match line Comparator Valid bit Ternary CAM Priority encoder.

Operation: How CAM performs search and write

CAM operation is typically described in two phases: programming (write) and search (read/lookup).

Write / program mode

Writing a CAM row typically loads the stored bits for that entry:

1. Select the target row.
2. Drive the desired stored data bits into the associative storage elements.
3. Optionally set/clear the valid bit.

CAM write circuits are designed to update stored pattern state without requiring full associative evaluation for every write.

Search / lookup mode

For a lookup:

1. The search key is broadcast to the array’s comparison circuitry (often to each column’s compare input).
2. Each row’s match logic evaluates whether its stored pattern equals (or satisfies the matching rules for) the key.
3. Match line signals assert for rows that match.
4. A priority encoder may convert multiple assertions into a single match index.
5. Output is presented as one-hot or encoded index, sometimes with additional metadata.

Timing intuition

• The associative compare happens in parallel across rows.
• The critical path typically includes match-line evaluation delay plus output encoding delay (or bank output aggregation).

Key learning terms: CAM Match line One-hot output Priority encoder Valid bit.

Example: Ternary CAM with valid bits (conceptual logic)

A ternary CAM stores, per entry and per bit position, both a value bit and a “don’t care” indicator (often encoded as X/Mask). The comparison rule commonly becomes:

• If a stored bit is marked “don’t care” ($X$), then it matches either $0$ or $1$ from the key.
• Otherwise, the stored value must equal the key bit.

At the row level, the row match is the AND across all bit positions, combined with the row’s valid bit.

Key learning terms: Ternary CAM Valid bit Match line One-hot output Priority encoder.