Explaining Different Addressing Modes in Computer Architecture

Addressing modes specify how an instruction determines the effective memory address (or operand value) it will use. Different CPU designs and instruction sets offer different modes to support efficient access patterns—e.g., constants (immediate), variables (direct), arrays (indexed), pointers (indirect), and relocatable code (PC-relative). These modes are central to understanding instruction encoding, execution, and performance tradeoffs.

Key idea: an addressing mode typically transforms an instruction’s encoded fields (register numbers, immediates, displacement, etc.) into an effective address used to fetch/store memory, or directly produces the operand value.

Mermaid overview of common categories:

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Core vocabulary (used throughout)

• effective address (EA): EA is what the CPU uses for the actual memory read/write.
• displacement: Often encoded in the instruction.
• base register: Common in base+offset modes.
• index register: Common in indexed modes.

1) Immediate addressing mode

In immediate addressing, the operand value is encoded directly in the instruction stream (as a literal constant). No additional memory address computation is needed.

• How it works: operand = immediate field
• Typical uses: loading constants, arithmetic with constants, comparisons against constants
• Encoding intuition: the instruction contains the constant bits; the CPU uses them directly.

Example semantics:

• ADD R1, R2, #5 → R1 = R2 + 5

2) Register addressing mode

In register addressing, the operand comes from a register, not from memory.

• How it works: operand = register contents
• Typical uses: register-register ALU operations, fast operand access
• Benefit: avoids memory latency

Example semantics:

• ADD R1, R2, R3 → R1 = R2 + R3 (both operands from registers)

3) Direct (absolute) addressing mode

In direct (sometimes called absolute) addressing, the instruction encodes a memory address directly.

• How it works: EA = address/immediate field (literal address)
• Typical uses: accessing fixed locations (e.g., memory-mapped I/O in some architectures)
• Limitation: code may not be easily relocatable if absolute addresses are used

Example semantics:

• LOAD R1, [0x1000] → load from memory address 0x1000

4) Indirect addressing mode

In indirect addressing, the instruction provides a pointer location (often a register), and the operand is fetched from memory at that pointer.

Two common variants:

• Register-indirect: EA = contents of a register

• Memory-indirect: instruction refers to a memory location whose contents are then treated as a pointer

• How it works (register-indirect): EA = Rk

• Typical uses: pointer dereferencing, implementing linked structures

Example semantics:

• LOAD R1, [R2] → R1 = MEM[ R2 ]

5) Indexed addressing mode (base/index + displacement)

Indexed addressing computes EA by combining:

• a base register and/or index register,
• optional scaling (e.g., multiplying index by element size),
• and a displacement (constant offset).

Common mathematical pattern:

Typical uses:

• array element access
• iterating through structured data
• efficient addressing without extra arithmetic instructions

Example semantics (conceptual):

• LOAD R1, [base + index*4] → element access for 4-byte words

6) Base + displacement (a special case of indexed)

A very common addressing mode family is base + displacement, often used because it’s compact to encode.

• How it works: EA = base + displacement
• Typical uses: stack frames, local variables, accessing fields at known offsets

Example semantics:

• LOAD R1, [BP + -8] → load local variable at offset from frame/base pointer

7) PC-relative addressing mode

In PC-relative addressing, EA is computed relative to the program counter (PC), enabling position-independent behavior (or easier relocation).

A common form:

• How it works: displacement is encoded in the instruction; PC supplies the anchor
• Typical uses: branches and jumps (though those often have their own encodings), global data references in position-independent code, jump tables in some designs
• Advantage: code can move in memory with fewer fixups

Example semantics:

• LOAD R1, [PC + offset] → read from a location near the current instruction

8) Auto-increment / auto-decrement addressing

These modes combine memory access with automatic update of a pointer register.

Two classic variants:

• Auto-increment: use EA = Rptr, then update Rptr = Rptr + step

• Auto-decrement: update first or after depending on ISA, then use EA

• How it works: reduces instruction count for sequential traversal (e.g., copying arrays)

• Typical uses: block moves, stream processing, iterating through lists

Example semantics (auto-increment):

• LOAD R1, [R2+] → R1 = MEM[R2], then R2 = R2 + step

9) Scaled indexed addressing (index * scale)

Many ISAs support a scale factor so that array indexing matches element sizes (e.g., 1, 2, 4, 8 bytes).

Pattern:

• Why it matters: avoids explicit multiplication instructions
• Typical scale values: limited set (e.g., powers of two) for encoding compactness

10) Addressing modes and instruction formats (how encoding relates)

Addressing modes show up as fields in the instruction encoding:

• register specifiers (e.g., r1, r2)
• immediates (literal constants or displacements)
• mode bits or opcode variants (to choose the addressing interpretation)

A helpful way to reason:

• Mode choice determines what the CPU treats as a “pointer,” a “literal,” or a “computed offset.”
• The CPU then computes EA (if needed) and performs the memory access.

Mermaid: dataflow perspective: