Common-Bus Multiplexers for 16×32-bit Register File
A common bus that can transfer data from any one of registers to a shared -bit bus is typically built using multiplexers: each bus bit is produced by selecting one register’s corresponding bit. A multiplexer (MUX) requires select lines determined by the number of inputs. For an -to-1 multiplexer, the number of selection inputs (select lines) is (so must be a power of 2 for standard binary selection). 2
Key terms: common bus register file multiplexer select lines.
Footnotes
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Multiplexer (digital electronics) - Wikipedia - Defines multiplexer input/output selection concept and select-line relationship for input sizes. ↩
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Logarithm properties (log base 2 for powers of two) - General definition of and the power relationship. ↩
Determine MUX selection inputs and MUX size
- 1Step 1
There are registers, so for each bus bit position you must select one of register inputs to drive that bus bit. This means a -to- multiplexing function per bit.
- 2Step 2
For an -to- multiplexer, the number of selection inputs is . With , .
- 3Step 3
The bus is bits wide, so you need the selection to happen independently for each bit position. Therefore you use multiplexers in parallel, each handling one bit (or equivalently, a single conceptual -bit-wide -to- MUX built from bit-slices).
(i) How many selection inputs are there in each multiplexer?
Since there are registers feeding the bus, each bus bit uses a -to-1 multiplexer. The number of select lines is:
So each multiplexer needs 4 selection inputs. 2
Footnotes
-
Multiplexer (digital electronics) - Wikipedia - Defines multiplexer input/output selection concept and select-line relationship for input sizes. ↩
-
Logarithm properties (log base 2 for powers of two) - General definition of and the power relationship. ↩
(ii) What size of multiplexers is needed?
Each register contains 32 bits, and the bus carries 32 bits, so the multiplexing must be performed for each bit position.
- Per bit position: a -to-1 MUX is needed.
- Bus-wide: this is replicated across 32 bit positions.
So the required configuration is:
- 32 parallel multiplexers, each of size -to-1 (1-bit wide), or equivalently
- a 32-bit-wide -to-1 multiplexer implemented as 1-bit slices.
This directly matches the idea that bus width multiplies the number of independent bit-slice multiplexers needed.
Footnotes
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Register-transfer logic / bus architecture overview (common bus and multiplexers) - Background on buses as shared communication paths and typical implementation concepts using selection/routing to avoid contention. ↩
Multiplexer requirements for the common bus
Per bus bit you need 16-to-1 selection; across 32 bus bits you need 32 such bit-slices.
Pro Tip
Always compute select lines from where is the number of inputs the MUX can choose from. Then multiply by bus width (bit-slices) when the bus is wider than 1 bit.
Common pitfall
Don’t confuse the bus width (32 bits) with the number of multiplexer inputs (16 registers). The selection lines depend on the number of sources (), not the bus width ().
Quick checks and edge cases
From registers to bus using MUX multiplexing
Choose source register
1Select the one register among using select lines."
Route each bit position
2For each of the bit positions, route the selected register bit to the bus."
Form the 32-bit bus value
3The outputs of all bit-slices combine to form the full 32-bit bus word."
Common-Bus MUX Flashcards
Knowledge Check
A common bus connects 16 registers using multiplexers. Per bus bit, the required multiplexer is best described as: