Clocked SR Flip-Flop Using a Master–Slave Flip-Flop: Explanation, Timing, and Truth-Table Reasoning

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Nov 4, 2026

A SR flip-flop is the basic memory element controlled by S and R. An SR latch is typically level-sensitive, meaning it can change output whenever its enable/clock level permits, which can create the race problem when a clock is used directly.

A clocked SR flip-flop is designed so that the outputs update at a safer time (often modeled as edge-triggered). One classic construction to achieve this is the master–slave flip-flop: a master latch captures inputs during one clock phase, and a slave latch transfers the captured value to the output during the opposite phase, preventing “simultaneous” feedback from causing indeterminate race outcomes.

Mermaid overview of the idea:

Key terms:

race condition
edge-triggering
level-sensitive latch

⚠️ Note: Many textbooks describe master–slave as producing behavior equivalent to edge-triggering, even though internally it uses level-sensitive latches with phased enables.

Master–Slave Flip-Flop (Conceptual Explanation)

Why an SR latch can race under clocking

An SR latch has two cross-coupled elements, so feedback is immediate. If you build a “clocked SR latch” by simply gating the SR inputs with the clock (or enable) and letting the same latch both (a) accept S/R changes and (b) resolve feedback during the same clock level, then S/R may change while Q is also changing, producing ambiguity in the intermediate time.

The master–slave architecture avoids that by ensuring:

During one clock phase, only the master responds to S/R; the slave output is effectively isolated.
During the other clock phase, the master is isolated, and only the slave responds—now using the stable master state.

Master–slave SR flip-flop: structure and phased operation

A typical master–slave SR flip-flop uses two SR latches:

Master latch enabled when the clock is in one state (e.g., $clk=1$ ).
Slave latch enabled when the clock is in the opposite state (e.g., $clk=0$ ), often via inverted clock or complementary enable signals.

Let:

Master outputs be $(Q_m, \overline{Q}_m)$
Final outputs be $(Q, \overline{Q})$

During master-active phase:

Slave is disabled → output holds (no transfer).
Master updates based on $(S, R)$ .

During slave-active phase:

Master is disabled → $(Q_m, \overline{Q}_m)$ stay constant.
Slave updates to match the stored master value → outputs change.

Key terms:

transfer window
enable gating
complementary clock phases

Walkthrough: From SR inputs to clocked output using master–slave

1
Step 1
When the clock is at the master’s active level, the master SR latch responds to $S$ and $R$ and updates $(Q_m, \overline{Q}_m)$ . Because the slave is disabled, the external output $(Q, \overline{Q})$ holds its previous state.
2
Step 2
When the clock switches to the slave’s active level, the master stops responding, freezing $(Q_m, \overline{Q}_m)$ . The slave latch is now enabled and transfers that stored master value to the outputs $(Q, \overline{Q})$ .
3
Step 3
If you view the moment the clock switches from one phase to the other as the “update edge,” the output effectively changes once per cycle, using the master’s captured value from the previous phase.
4
Step 4
If $S=1$ and $R=1$ simultaneously, the SR latch is invalid/indeterminate. In a master–slave, this invalidity can still propagate when the slave is enabled, so system design must avoid $S=R=1$ .
5
Step 5
If $S=0$ and $R=0$ , the master retains its state during its phase; then the slave transfers (or retains) that same state during its phase, yielding stable outputs.

Mapping SR latch behavior into a clocked SR flip-flop

For an SR latch, the usual behavior (conceptually) is:

$S=1, R=0$ → set: $Q=1$
$S=0, R=1$ → reset: $Q=0$
$S=0, R=0$ → hold previous state
$S=1, R=1$ → invalid (often leads to race/indeterminate state)

A clocked SR flip-flop using master–slave preserves the same logical outcomes for each valid input pattern, but the time when $Q$ updates is governed by the transfer phase.

Mermaid timing intuition:

Clocked SR flip-flop behavior by (S,R) with master–slave transfer

Conceptual: Q updates only during the slave (transfer) phase; S/R validity is from SR latch rules.

Pro Tip: Think in two steps—capture then transfer

For any clocked SR flip-flop implemented as master–slave, first ask: “What does the master latch capture this phase?” Then ask: “When does the slave transfer it?” This mental model prevents most timing/race confusion.

Warning: $S=R=1$ must be avoided

In SR latch logic, $S=1$ and $R=1$ is typically invalid and can drive indeterminate behavior. Master–slave does not “fix” invalid SR combinations—it only shifts when they may affect outputs.

One clock cycle: capture (master) vs transfer (slave)

Master captures

Clock Phase A

Master enabled; outputs hold; $S,R$ determine $(Q_m,\overline{Q}_m)$ . "

Roles swap

Clock Transition

Master disables and slave enables (often modeled as an edge for system-level behavior)."

Slave transfers

Clock Phase B

Slave enabled; outputs update to match $(Q_m,\overline{Q}_m)$ . "

Common conceptual FAQs

Inputs:
  S R
Cases:
  0 0 -> hold (during transfer)
  1 0 -> set to 1 (during transfer)
  0 1 -> reset to 0 (during transfer)
  1 1 -> invalid/indeterminate

Clocked behavior:
  Q updates during the slave-enabled phase to match master state captured in the prior phase.

Master–Slave Clocked SR Flip-Flop (Quick Check)

1 / 5

Question · Term

What does the master latch do?

Click to reveal

Answer · Definition

It captures $S$ and $R$ during its enabled clock phase and stores $(Q_m,\overline{Q}_m)$ .

Knowledge Check

Question 1 of 3

Q1Single choice

In a master–slave SR flip-flop, when does the external output Q update?

During the master’s enabled clock phase

During the slave’s enabled (transfer) clock phase

Only when S and R both change at the same time

Continuously whenever the clock is high

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