Virtual Memory: Logical vs Physical Addresses and Address Translation
Virtual memory keyword (VM) allows each process to see its own private, large address space, even though the machine has limited physical RAM keyword (PM). The operating system and hardware cooperate to translate each program’s logical (virtual) address into a physical address used to access RAM, typically using paging and the Memory Management Unit (MMU) keyword.2
A logical address is what the program generates (e.g., instruction/data references). A physical address is where the MMU ultimately sends the request to the memory system. In a paged system, a logical address is split into a page number and page offset; the page number is translated through page tables into a page frame number, then recombined with the same offset to form the physical address.
Mermaid view of the translation pipeline:
This translation is the core role of virtual memory: memory references remain simple for software (use virtual addresses), while the OS can map, protect, and swap/evict pages transparently.3
Key terms:
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Footnotes
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"Virtual memory" (Wikipedia) https://en.wikipedia.org/wiki/Virtual_memory - Overview of virtual memory, address translation, and paging concepts. ↩ ↩2 ↩3
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"Paging" (Wikipedia) https://en.wikipedia.org/wiki/Paging - Explains pages/frames, page tables, and address translation structure. ↩ ↩2
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"Translation Lookaside Buffer" (Wikipedia) https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer - Describes TLB purpose and relationship to page-table walking. ↩
Virtual Memory & Address Translation (Logical to Physical)
Logical vs physical address: what changes, what stays
In a typical paged architecture, the logical address structure is:
- Logical address =
- Physical address =
Only the page number changes during translation; the page offset remains the same because the page and frame sizes match.
A concrete decomposition helps: if pages are size , then the lowest bits of the logical address are the page offset, and the remaining bits identify the virtual page. After translation, the virtual page number becomes a physical frame number, and the offset is appended unchanged.2
Mermaid diagram of bit decomposition + remapping:
Key terms for this section:
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Footnotes
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"Virtual memory" (Wikipedia) https://en.wikipedia.org/wiki/Virtual_memory - Overview of virtual memory, address translation, and paging concepts. ↩ ↩2
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"Paging" (Wikipedia) https://en.wikipedia.org/wiki/Paging - Explains pages/frames, page tables, and address translation structure. ↩
How virtual memory works (paging, page tables, and page faults)
At a high level, virtual memory is implemented by:
- Dividing virtual memory into pages and physical memory into frames keyword.
- Maintaining a page table that maps each virtual page to a physical frame (or marks it as not present) keyword.2
- On each memory access, the MMU consults the page table (often via a TLB first) to find the physical frame for the virtual page.2
- If the referenced page is not present, the CPU triggers a page fault, and the OS loads the needed page from disk (or zero-fills for demand-zero pages).2
Important: page faults are a mechanism for demand paging, meaning pages are brought into RAM only when first used.
Key terms:
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Footnotes
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"Virtual memory" (Wikipedia) https://en.wikipedia.org/wiki/Virtual_memory - Overview of virtual memory, address translation, and paging concepts. ↩ ↩2
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"Paging" (Wikipedia) https://en.wikipedia.org/wiki/Paging - Explains pages/frames, page tables, and address translation structure. ↩ ↩2 ↩3 ↩4
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"Translation Lookaside Buffer" (Wikipedia) https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer - Describes TLB purpose and relationship to page-table walking. ↩ ↩2
Logical-to-Physical Address Translation in a Paged Virtual Memory System
- 1Step 1
The running process issues a read/write to an address in its virtual address space (logical address).
- 2Step 2
The MMU partitions the logical address into a virtual page number (VPN) and a page offset using the page size.
- 3Step 3
If the TLB contains an entry for the VPN, it provides the mapped physical frame number (PFN) quickly.
- 4Step 4
On a TLB miss, the MMU uses the process page table to look up the PFN or determine that the mapping is absent.
- 5Step 5
If the page is not present, a page fault occurs; the OS loads (or creates) the page and updates the page tables.
- 6Step 6
Once PFN is known, the MMU concatenates PFN with the same page offset to form the physical address and completes the memory access.
Pro Tip: Offsets often never change
In paging, the page/frame size is constant, so the page offset portion of a logical address is reused as-is in the physical address. Translation typically concerns the page number only.
Footnotes
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"Virtual memory" (Wikipedia) https://en.wikipedia.org/wiki/Virtual_memory - Overview of virtual memory, address translation, and paging concepts. ↩
Warning: Translation isn’t free—TLBs exist to reduce the cost
Page tables can be large, so repeated lookups would be expensive. A TLB caches recent translations, reducing average translation time. Without caching, memory accesses would suffer frequent page-table walks.
Footnotes
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"Translation Lookaside Buffer" (Wikipedia) https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer - Describes TLB purpose and relationship to page-table walking. ↩
Role of logical address in OS features: isolation and protection
Virtual memory makes logical addresses a natural boundary for isolation:
- Per-process address spaces: each process’s logical addresses map to different physical frames, preventing unintended access.2
- Memory protection: page tables store permission metadata (e.g., read/write/execute, user/supervisor). The MMU uses it during translation to enforce access control.2
- Contiguity illusion: a process can use a contiguous virtual address range even when physical frames are scattered.
These properties emerge because software typically reasons in terms of logical addresses while hardware enforces mappings at translation time.2
Role of physical address: resource location and system-level control
Physical addresses represent actual RAM locations. Their role includes:
- Mapping outcomes: the page table (indirectly) determines which physical frames back each logical page.
- Sharing and copy-on-write (conceptual): multiple logical pages may map to the same physical frame depending on OS policies (e.g., during program start, memory sharing, or copy-on-write).
- Accounting and performance: the OS can measure physical memory usage, decide evictions, and manage free frames because physical addresses correspond to real resources.2
Key terms:
- keyword
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Footnotes
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"Virtual memory" (Wikipedia) https://en.wikipedia.org/wiki/Virtual_memory - Overview of virtual memory, address translation, and paging concepts. ↩ ↩2 ↩3 ↩4 ↩5
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"Paging" (Wikipedia) https://en.wikipedia.org/wiki/Paging - Explains pages/frames, page tables, and address translation structure. ↩ ↩2 ↩3 ↩4 ↩5
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"Translation Lookaside Buffer" (Wikipedia) https://en.wikipedia.org/wiki/Translation_Lookaside_Buffer - Describes TLB purpose and relationship to page-table walking. ↩
Where time can be spent during address translation
Conceptual comparison: cached translation is fastest; page-table walk is slower; page fault dominates.
End-to-End Memory Reference Lifecycle (Virtual Memory)
Virtual Address Reference
1Program issues a load/store using a logical (virtual) address."
Hardware Translation
2MMU translates VPN to PFN using TLB and then page tables."
Access Physical Memory
3Physical address is formed and RAM is accessed if the page is present."
Optional Page Fault Path
4If not present, OS loads/creates the page, updates page tables, then retries."
Common confusions and edge cases
Virtual Memory Core Concepts
Knowledge Check
In a paged virtual memory system, which part of a logical address is typically reused unchanged in the physical address?