Signed Number Representation: Sign-Magnitude, 1’s Complement, and 2’s Complement

Signed number representations encode negative integers in binary by dedicating meaning to the most significant bit(s) and by defining arithmetic rules for addition/subtraction. The three classical schemes are:

• Sign-magnitude: sign bit + magnitude bits.
• One’s complement: yields two zeros.
• Two’s complement: yields a single zero and enables straightforward addition.

A conceptual view is: each representation defines (1) how to encode values into $n$ bits and (2) what binary addition does with encoded operands. In hardware, the key practical goal is to make addition logic uniform and simple across signs, while minimizing special cases like multiple zeros or extra correction steps.

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Core definitions to keep consistent

• MSB is typically the sign-related bit.
• Bitwise complement defines one’s complement negativity.
• Carry/overflow affects meaning near limits.

How each scheme represents negatives (encoding rules)

1) Sign-magnitude

In an $n$-bit word:

• The sign bit determines polarity: typically $0$ for nonnegative, $1$ for negative.
• The remaining $n-1$ bits store the absolute value (“magnitude”).

If $x \ge 0$, encode magnitude directly. If $x < 0$, encode the magnitude and set the sign bit to $1$.

Consequence: arithmetic must explicitly handle differing sign bits; raw unsigned addition does not directly equal signed addition.

2) One’s complement

Define nonnegative $x$ normally in $n$ bits. To represent a negative value:

• Compute the bitwise complement of the positive representation.

Equivalently, if $P$ is the $n$-bit pattern for $+x$, then the $n$-bit pattern for $-x$ is $\overline{P}$.

Consequence: there are two encodings for zero:

• $+0$ is all zeros.
• $-0$ is all ones.

Addition also has a special rule: if there is a carry out of the most significant bit, it must be added back (“end-around carry”)—this is a correction step not present in two’s complement.

3) Two’s complement

Again, encode nonnegative $x$ normally. For negative values:

• Take the one’s complement and add $1$.

Equivalently: if $P$ is the $n$-bit pattern for $+x$, then $-x$ is the bitwise complement of $P$ plus $1$ (modulo $2^n$).

Consequence: there is a single zero representation (all zeros), and addition can use standard binary adders with wraparound; the hardware behavior corresponds to signed arithmetic interpretation within the representable range.

Visualizing the bit patterns around zero

Even without choosing an explicit bit-width, each scheme’s “shape” differs near zero and affects arithmetic correctness and simplicity.

Advantages and disadvantages (deep, engineering-focused)

Sign-magnitude

Advantages

1. Direct interpretability: you can interpret magnitude and sign separately.
2. Negation operation can be as simple as flipping only the sign bit (with magnitude unchanged).

Disadvantages

1. Two encodings of zero: both “+0” and “−0” exist, which complicates equality checks and some arithmetic edge cases.
2. Arithmetic complexity: standard addition of bit patterns does not directly correspond to signed addition across sign changes without additional handling.
3. Overflow behavior is less “natural” for pure adder hardware; designers typically prefer representations where the same adder works for signed addition.

One’s complement

Advantages

1. Negation via bitwise NOT: $-x$ is the bitwise complement of $+x$.
2. Addition hardware can be close to standard addition, but with one correction conceptually tied to end-around carry.

Disadvantages

1. Two zeros persist: $+0$ and $-0$ both exist.
2. End-around carry correction: addition requires an additional step when there is carry out, complicating circuits compared with two’s complement.
3. Some comparison and normalization logic can become more intricate because of the second zero representation.

Two’s complement

Advantages

1. Single zero eliminates ambiguity and simplifies equality/edge-case logic.
2. Uniform addition: two’s complement arithmetic corresponds to standard binary addition modulo $2^n$, and overflow can be detected/handled using sign-bit rules.
3. Hardware efficiency: widely supported by CPU/ALU design.

Disadvantages

1. Asymmetric range: for $n$ bits, the representable range is typically $-2^{n-1}$ to $2^{n-1}-1$, so the negative side has one extra magnitude compared with positive.
2. Overflow wraparound: two’s complement addition “wraps” in the modular sense, so overflow detection is necessary for correctness in bounded arithmetic.
3. Negation not just sign flip: while there are fast methods, negating in general involves the complement plus one rule, not just flipping a single bit (unlike sign-magnitude’s simple sign-bit flip).