Paging (Memory Management): Short Notes for OS Examinations
Paging is a keywordmemory management scheme that introduces an indirection layer between logical (virtual) addresses and physical (main-memory) addresses by using fixed-size keywordpages and keywordframes.2
With keywordpaged virtual memory, the operating system can make a program appear to have a large, contiguous address space even though the corresponding physical frames may be scattered—and some pages may reside on secondary storage until needed.2
Footnotes
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Memory paging - Wikipedia - Defines paging and its role in paged virtual memory. ↩ ↩2
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Paging - GeeksforGeeks - Explains pages/frames, mapping, and key benefits. ↩ ↩2
Paging and Virtual Memory (Conceptual Overview)
Core idea in one line (what you write in an exam)
A process address space is split into fixed-size keywordpages, physical memory into equally sized keywordframes, and a keywordpage table maps each page to the frame containing its contents.3
Key benefits (often cited):
- Avoids external fragmentation because allocation is in fixed-size blocks.2
- Supports larger programs by keeping only needed pages in RAM (demand/paged virtual memory).
Footnotes
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Memory paging - Wikipedia - Defines paging and its role in paged virtual memory. ↩ ↩2 ↩3
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Paging - GeeksforGeeks - Explains pages/frames, mapping, and key benefits. ↩ ↩2
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Page table - Wikipedia - Explains role of page table and PTE mappings. ↩
Address Translation Lifecycle in a Paged System
Virtual address created
1) Process issues memory referenceCPU generates a virtual address (virtual page number + offset)."
MMU consults TLB/page table
2) TranslationHardware translates to a physical frame; TLB may provide fast cached translations."
Page fault
3) If missingIf the page isn’t present/mapped, a page fault exception is raised."
Load & update
4) OS actionOS loads the page from secondary storage, updates the PTE, then resumes execution."
Instruction continues
5) RetryAccess is re-attempted with the now-valid mapping."
How paging uses a page table (short explanation)
The keywordpage table entry (PTE) stores the mapping from virtual pages to physical frames, plus status/permission bits (e.g., whether the page is present).
In multi-process systems, each process has its own logical address space; therefore, identical virtual addresses from different processes can map to different physical frames, which the page table handles.
Footnotes
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Page table - Wikipedia - Explains role of page table and PTE mappings. ↩ ↩2
Page Fault Handling (Major Fault Path)
- 1Step 1
A page fault exception traps execution to the OS kernel, saving enough state to resume later.
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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- 2Step 2
OS checks whether the faulting address is legal for the process; invalid access leads to an error/termination.
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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- 3Step 3
OS determines where the needed page is stored (e.g., swap area/page file or executable storage).
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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- 4Step 4
If no free frame exists, OS runs a keywordpage replacement algorithm to choose a victim frame.
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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- 5Step 5
OS performs disk I/O to read the required page into the chosen physical frame (slow compared to RAM).
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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- 6Step 6
OS updates the PTE (e.g., frame number and present bit) and resumes the faulting instruction.
Footnotes
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
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TLB and why translation must be fast
A keywordTLB (Translation Lookaside Buffer) is a hardware cache that stores recent virtual→physical address translations to avoid frequent page-table lookups.2
- If the translation is in the TLB: TLB hit → fast access.
- If not: TLB miss → hardware performs a page table walk; if the page is not present, the CPU triggers a page fault.
Footnotes
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Translation lookaside buffer - Wikipedia - Defines TLB and hit/miss/page walk/page fault behavior. ↩ ↩2
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Paging: Faster Translations (TLBs) - OSTEP PDF - OSTEP notes on TLB as an address-translation cache in the MMU. ↩
Exam-ready phrasing
Write: “Paging divides virtual memory into pages and physical memory into frames; the page table maps page numbers to frame numbers. If a referenced page is not in RAM, a page fault occurs and the OS loads it from disk, updates the PTE, and resumes execution.”3
Footnotes
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Memory paging - Wikipedia - Defines paging and its role in paged virtual memory. ↩
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Paging - GeeksforGeeks - Explains pages/frames, mapping, and key benefits. ↩
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Page Fault Handling - GeeksforGeeks - Step-by-step fault handling including frame allocation, disk I/O, and PTE update. ↩
Common confusion: paging vs fragmentation
Paging largely avoids external fragmentation by using fixed-size frames, but it can introduce keywordinternal fragmentation when a page/frame is larger than the data needed.2
Footnotes
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Paging - GeeksforGeeks - Explains pages/frames, mapping, and key benefits. ↩
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Internal vs. External Fragmentation in Paging - Baeldung - Explains why paging can cause internal fragmentation. ↩
Trade-offs in Paging (What to Mention in Notes)
Paging improves allocation/contiguity issues but may add overhead (translation + faults).
Quick Notes to Memorize
Paging Short Notes (Self-Check)
Knowledge Check
In paging, a virtual address is translated using which structure?