Micro-operations Control Word Design for a 16-Register Bus CPU

This section designs a micro-operation control word for a simple bus-based datapath containing:

• 16 registers connected to a common bus
• an ALU that supports 32 operations
• a shifter that supports 8 operations

Key idea: in a single micro-cycle, the bus typically carries one source register value into the ALU/shifter, and the ALU/shifter result is written into one destination register. The control word therefore must include bit-fields to:

1. select the source register placed on the bus,
2. select the destination register to be written,
3. select which ALU or shifter operation to perform.

We denote a micro-operation as something like: $R_d \leftarrow \text{ALU}(R_s, R_t)$ but in a bus design, $R_s$ is selected to drive the bus, while $R_t$ is commonly taken from a second internal path/register or from another selected bus time. Since the question asks for the bit fields to specify the micro-operation $R4 \leftarrow R5 + R6$, we will allocate sufficient bits for register selection and ALU operation, plus a one-bit “functional unit select” (ALU vs shifter) to be explicit.

Required selector bit-widths

For a selector with $N$ choices, the number of bits is: $\lceil \log_2 N \rceil$

So:

• Register selectors for 16 registers: $\lceil \log_2(16)\rceil = 4$ bits
• ALU operation selectors for 32 ops: $\lceil \log_2(32)\rceil = 5$ bits
• Shifter operation selectors for 8 ops: $\lceil \log_2(8)\rceil = 3$ bits

We also include:

• A 1-bit field to choose ALU vs shifter (otherwise the shifter/ALU fields would overlap ambiguously)

Mermaid sketch of the datapath intent:

Keywords: micro-operation control word bus ALU shifter.

(i) Formulate a control word for micro-operation

We define a control word structured as fields:

1. Source register select (bus input)
   • $4$ bits: selects which of $R0 \ldots R15$ appears on the bus
2. Destination register select (write register)
   • $4$ bits: selects $R_d$ to receive the result
3. Functional unit select
   • $1$ bit: 0 = ALU, 1 = Shifter
4. ALU operation select
   • $5$ bits: chooses one of 32 ALU operations (e.g., ADD, SUB, AND, OR, …)
5. Shifter operation select
   • $3$ bits: chooses one of 8 shifter operations (e.g., logical shift left/right, arithmetic shift, rotate, …)

Total control word length

$4 + 4 + 1 + 5 + 3 = 17 \text{ bits}$

We now present the control word format.

Control Word Bit Layout (example convention)

Let the control word be:

So the control word is: $C = \underbrace{R_s[3:0]}_{4}\ \underbrace{R_d[3:0]}_{4}\ \underbrace{U}_{1}\ \underbrace{\text{ALUop}[4:0]}_{5}\ \underbrace{\text{Shop}[2:0]}_{3}$

Micro-operation meaning

• The selected source register $R_s$ is placed onto the bus.
• The functional unit selected by $U$ performs the selected operation.
• The output is written into destination register $R_d$.

[Pro tip]{type="tip"}: When designing control words, it’s common to include unused fields for the inactive unit (ALU vs shifter). They may be don’t-cares in optimization, but it’s clean to allocate fixed bit-fields as done above.
[/Pro tip]

(ii) Show the bits of the control word for $R4 \leftarrow R5 + R6$

We must map $R4 \leftarrow R5 + R6$ to control fields.

• Destination register: $R_d = R4$
• Source register (bus input): $R_s = R5$

Now: the operation is addition, so we choose:

• Functional unit: ALU, therefore $U=0$
• ALU operation code: choose the binary code for ADD among 32 ALU ops.

However, the question does not provide the numeric mapping of “ADD” to a specific 5-bit code. In such problems, either:

• the ADD opcode is assumed to be $00000$ (often “first” operation), or
• the answer expresses the field as “ALUop = (ADD’s 5-bit code)”.

To produce a fully explicit bit pattern, we adopt the standard teaching convention:

• ALU ADD corresponds to ALUop = 00000 (i.e., ADD is opcode 0)

If your course uses a different opcode mapping, only the ALUop[4:0] bits change; the register select bits remain the same.

Convert register indices to 4-bit binary

• $R5 = 0101$
• $R4 = 0100$

Assemble the control word

Using the layout $[16:13]=R_s,\ [12:9]=R_d,\ [8]=U,\ [7:3]=\text{ALUop},\ [2:0]=\text{Shop}$:

• $R_s=R5 \Rightarrow 0101$
• $R_d=R4 \Rightarrow 0100$
• $U=0$ (ALU active)
• $\text{ALUop}=00000$ (ADD assumed)
• $\text{Shop}=xxx$ (unused when $U=0$); for a concrete value we set $\text{Shop}=000$

So: $C = \underbrace{0101}_{R_s}\ \underbrace{0100}_{R_d}\ \underbrace{0}_{U}\ \underbrace{00000}_{\text{ALUop}}\ \underbrace{000}_{\text{Shop}}$

Written as a 17-bit string: $C = 0101\ 0100\ 0\ 00000\ 000$

Or concatenated: $C = 01010100000000000$

[Warning]{type="warning"}: If your curriculum assigns a different 5-bit opcode to the ALU’s ADD operation, replace only the $\text{ALUop}[4:0]$ field. The $R_s$ and $R_d$ fields ($0101$ and $0100$) do not change.
[/Warning]

Mermaid: field decoding view

Keywords: ALU operation code opcode binary encoding don’t-care.