IO Device Interfaces: Short Notes (Two Topics)

Input/Output (I/O) device interfaces define how the CPU and an I/O device communicate over a system bus—covering addressing, data transfer, synchronization, and signaling. Two common interface mechanisms are: Programmed I/O (Port I/O / Memory-mapped I/O) and Interrupt-based I/O (often combined with DMA in advanced systems).
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Note: You asked for “any two” short notes; the course section below provides two complete short notes: (1) Port I/O vs Memory-mapped I/O and (2) Interrupt-driven I/O (with optional DMA context).

Short Note 1 — Port-Mapped I/O vs Memory-Mapped I/O (Programmed I/O)

Programmed I/O is when software explicitly reads/writes device registers, typically by the CPU executing instructions that access an I/O address space or memory address space.

1) Port-mapped I/O (Paced by I/O instructions)

In port-mapped I/O, the CPU uses dedicated I/O instructions and addresses I/O ports rather than normal memory addresses. Each port corresponds to a device register (data, status, control). The device interface typically includes:

• Address decoding (which port/register is targeted)
• Read/write strobes (signals that qualify access)
• Data path (data bus into/out of the device)
• Status signaling (e.g., ready/not-ready)

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2) Memory-mapped I/O (MMIO)

In memory-mapped I/O, a device’s registers are assigned memory addresses. The CPU accesses the device by normal load/store operations to those addresses. The interface provides:

• MMIO address decoding (which address range belongs to the device)
• Read/write handling (mapping bus cycles to device register operations)
• Ordering/visibility considerations (to ensure software observes the correct device state)

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3) Comparison (typical exam points)

Short Note 2 — Interrupt-Driven I/O Interface (and DMA Context)

Instead of busy-wait polling, an I/O device can notify the CPU using an interrupt. This reduces wasted CPU cycles and improves responsiveness.

1) Interrupt signaling mechanism (interface view)

An interrupt interface typically includes:

• Interrupt request line (IRQ) or an interrupt message mechanism
• Interrupt controller that prioritizes and masks interrupts
• Interrupt acknowledgment so the CPU/device interface knows the request was accepted
• ISR (Interrupt Service Routine) executed by the CPU

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2) Typical interrupt-driven workflow

When the I/O device has data ready (or completed an operation), it asserts an IRQ. The CPU:

1. Saves context (as per architecture)
2. Jumps to the ISR
3. In the ISR, reads the device’s status/data registers
4. Clears the interrupt condition at the device (e.g., via control/status register)
5. Returns to normal execution

3) Why DMA often appears with interrupt I/O

Many devices transfer more data than is efficient to move byte-by-byte using programmed I/O. Therefore, systems often combine:

• Interrupts to indicate transfer completion or errors
• DMA to perform bulk transfer directly between device and memory

DMA interfaces add:

• Bus mastering / arbitration
• Transfer size and addressing
• Modes like burst/continuous transfers and flow control

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