Implement S-R, T, and D Flip-Flops Using a JK Flip-Flop (and State-Table Implementations)

A JK flip-flop is a universal sequential element whose next-state behavior is governed by its characteristic equation:
$Q_{n+1} = J\overline{Q_n} + \overline{K}Q_n \; .$ 2

We will use this equation (and the JK “operation modes”: hold/set/reset/toggle) to implement three other flip-flop behaviors by driving the JK inputs $J$ and $K$ with combinational logic built from the target inputs and the present state $Q_n$. 2

Key terms: JK flip-flop Characteristic equation Excitation/transition design.

Footnotes

1. electronicforu: JK Flip Flop Circuit, Truth Table, Limitations, and Uses - Provides the characteristic equation $Q(n+1)=JQ'_n+K'Q_n$. ↩ ↩²

2. CS UCR PDF: Latches and Flip-Flops (Flip-Flop notes) - States JK characteristic equation derivation and $Qnext=K'Q+JQ'$. ↩ ↩²

We’ll proceed in layers:

1. Define desired $Q_{n+1}$ behavior for S-R, T, and D.
2. Substitute into the JK characteristic equation to derive $J$ and $K$.
3. Validate with state tables (present-state $Q_n$ vs next-state $Q_{n+1}$).

We also use the practical mapping that the JK inputs correspond functionally to SR-style set/reset when exactly one of them is asserted, while $J=K=1$ causes toggle.

Footnotes

1. Electronics-Tutorials.ws: JK Flip Flop and Master-Slave JK Flip Flop Tutorial - Explains JK vs SR and toggle when both inputs are asserted. ↩

Target behaviors (state tables)

S-R (Set/Reset) flip-flop behavior

For a standard clocked SR flip-flop (no “invalid” simultaneous S and R):

• If $S=1, R=0$ then $Q_{n+1}=1$ (set)
• If $S=0, R=1$ then $Q_{n+1}=0$ (reset)
• If $S=0, R=0$ then $Q_{n+1}=Q_n$ (hold)
• If $S=1, R=1$ the behavior depends on the specific SR convention; in SR latches it is invalid, while JK resolves this via toggle. For our implementation, we will explicitly choose a safe mapping that avoids ambiguity by embedding the desired logic into JK. 2

T flip-flop behavior

A T flip-flop toggles when $T=1$ and holds when $T=0$, i.e.:

• If $T=0$: $Q_{n+1}=Q_n$
• If $T=1$: $Q_{n+1}=\overline{Q_n}$

D flip-flop behavior

A D flip-flop has next state equal to the input:

• $Q_{n+1}=D$ (independent of present state)

Key terms: Set Reset Toggle.

Footnotes

1. CS120b flipflops.pdf (same source section) - Notes SR undefined vs JK toggling when both inputs asserted. ↩

2. Electronics-Tutorials.ws: JK Flip Flop and Master-Slave JK Flip Flop Tutorial - Explains JK vs SR and toggle when both inputs are asserted. ↩

3. GeeksforGeeks: T Flip Flop - Gives T flip-flop behavior and characteristic equation $Q(n+1)=TQ'_n+T'Q_n$. ↩

4. GeeksforGeeks: D Flip Flop - States D flip-flop characteristic equation $Q_{n+1}=D$. ↩

1) Implement an S-R flip-flop using a JK flip-flop

A common functional conversion is to drive the JK inputs with the SR signals:

• $J = S$
• $K = R$

Then the JK characteristic equation yields the correct SR-style behavior:

• With $Q_n=0$: $Q_{n+1}=J\overline{Q_n}+\\overline{K}Q_n = J = S$
• With $Q_n=1$: $Q_{n+1}=\\overline{K} = \\overline{R}$ which equals 1 only when $R=0$.

This produces: set/hold/reset behavior when $(S,R)$ takes on the SR-valid combinations. 2

State table validation (S-R implementation)

Assume $J=S$, $K=R$.

For the remaining combination $S=1, R=1$, a JK flip-flop will toggle when both inputs are asserted ($J=K=1$).
So, if you must emulate a strictly “no-invalid-condition” SR device, avoid applying $S=R=1$ or add external gating to force it into a safe condition.

JK-to-SR mapping.

Footnotes

1. Electronics-Tutorials.ws: JK Flip Flop and Master-Slave JK Flip Flop Tutorial - Describes functional relationship of J like S and K like R (supports SR-style mapping). ↩ ↩²

2. electronicforu: JK Flip Flop Circuit, Truth Table, Limitations, and Uses - Provides the characteristic equation $Q(n+1)=JQ'_n+K'Q_n$. ↩

3. CS120b flipflops.pdf (same source section) - Notes SR undefined vs JK toggling when both inputs asserted. ↩

2) Implement a T flip-flop using a JK flip-flop

A T flip-flop is equivalent to a JK flip-flop with both inputs tied together:

• $J = T$
• $K = T$ 2

Then when $T=0$, $J=K=0$ ⇒ hold; when $T=1$, $J=K=1$ ⇒ toggle. 2

State table validation (T implementation)

Assume $J=K=T$.

Toggle (T).

Footnotes

1. GeeksforGeeks: T Flip Flop - Gives T flip-flop behavior and characteristic equation $Q(n+1)=TQ'_n+T'Q_n$. ↩ ↩²

2. Rohini College of Engineering PDF (T flip-flop section) - Provides T flip-flop next-state rules ($T=0$ hold, $T=1$ toggle). ↩

3. CS120b flipflops.pdf (same source section) - Notes SR undefined vs JK toggling when both inputs asserted. ↩

3) Implement a D flip-flop using a JK flip-flop

A D flip-flop requires:

• $Q_{n+1}=D$

One standard JK-to-D conversion is:

• $J = D$
• $K = \\overline{D}$

Verification via the JK characteristic equation:

• If $Q_n=0$: $Q_{n+1}=J\\overline{0}+\\overline{K}0=J=D$
• If $Q_n=1$: $Q_{n+1}=J\\overline{1}+\\overline{K}1=\\overline{K}=D$ because $\\overline{K}=\\overline{\\overline{D}}=D$.

So in all cases $Q_{n+1}=D$, independent of $Q_n$. 3

State table validation (D implementation)

[D storage]{def="Next-state equals input, $Q_{n+1}=D$, independent of present state"}.

Footnotes

1. GeeksforGeeks: D Flip Flop - States D flip-flop characteristic equation $Q_{n+1}=D$. ↩ ↩²

2. electronicforu/conversion table excerpt (JK/D relations) - Shows JK-style conversion patterns including JK-to-D mapping logic (contextualized in conversion discussion). ↩ ↩²

3. electronicforu: JK Flip Flop Circuit, Truth Table, Limitations, and Uses - Provides the characteristic equation $Q(n+1)=JQ'_n+K'Q_n$. ↩

Summary: J and K wiring for each target flip-flop

Key terms: Next-state State table Combinational driving.

Footnotes

1. Electronics-Tutorials.ws: JK Flip Flop and Master-Slave JK Flip Flop Tutorial - Describes functional relationship of J like S and K like R (supports SR-style mapping). ↩

2. GeeksforGeeks: T Flip Flop - Gives T flip-flop behavior and characteristic equation $Q(n+1)=TQ'_n+T'Q_n$. ↩

3. Rohini College of Engineering PDF (T flip-flop section) - Provides T flip-flop next-state rules ($T=0$ hold, $T=1$ toggle). ↩

4. electronicforu/conversion table excerpt (JK/D relations) - Shows JK-style conversion patterns including JK-to-D mapping logic (contextualized in conversion discussion). ↩