Finite-State Machines (FSM): A Short Note with Core Theory and Examples
A finite-state machine (FSM) is a mathematical model of computation used to describe systems with a limited number of modes (states). At each step, the machine reads an input symbol and updates its current state according to a transition rule. FSMs are especially important because they precisely capture the class of regular languages and appear in many practical designs like lexical analyzers, protocol logic, and digital circuits.
The formal structure is often given as a 5-tuple. A deterministic finite automaton (DFA) is commonly defined by: where is a finite set of states, is the input alphabet, is the transition function, is the start state, and is the set of accepting (final) states.
A DFA processes an input string by starting in and repeatedly applying to determine the next state; acceptance occurs if the final state after consuming the entire string lies in .
Key terms to remember
- state: one of the machine’s finite configurations
- alphabet
- transition function
- start state
- accepting state
Note: Many textbooks also describe nondeterminism (NFA) and show that NFAs and DFAs recognize the same class of languages (regular languages).
Pro Tip
When writing a short note, define the 5-tuple first (states, alphabet, transition, start, accepting) and then briefly explain how processing and acceptance work.
How an FSM runs on an input
Start
InitializePlace the machine in start state before reading input."
Transition step
Read symbolsFor each input symbol, update the state using ."
Accept/Reject
FinishAfter the last symbol, accept iff the current state is in ."
DFA vs NFA vs “output” FSMs (Mealy/Moore)
FSMs appear in multiple variants depending on determinism and whether outputs are produced during operation.
DFA vs NFA (nondeterminism)
- In a nondeterministic finite automaton (NFA) the transition function allows multiple next states for the same input symbol.
- The usual definition of acceptance for an NFA is existential: the input is accepted if at least one computation path ends in an accepting state after consuming the entire string.
Mealy vs Moore machines (FSM with outputs)
When an FSM produces outputs, it can be modeled as:
- A [Mealy machine]{def="FSM where outputs are associated with transitions}”: output depends on the current state and input symbol (on edges).
- A [Moore machine]{def="FSM where outputs are associated with states}”: output depends only on the current state (in nodes).
Why this matters
- In protocol/control systems, Mealy machines can react immediately to inputs (output on transition).
- In hardware design and control, Moore machines are often preferred for stable outputs tied to states.
Construct (and describe) an FSM for a simple language property
- 1Step 1
Example: recognize strings over {0,1} that contain an even number of 0s.
- 2Step 2
Use two states representing parity: (even # of 0s so far) and (odd # of 0s so far).
- 3Step 3
Start in because before reading input, the count of 0s is even.
- 4Step 4
On input 0: toggle parity (, ). On input 1: parity unchanged.
- 5Step 5
Accept in and reject in after the entire input is consumed.
Example short note (pattern-recognition style)
Here is a compact “short note” you can adapt:
A finite-state machine (FSM) is a formal model for computing with a finite number of states. A DFA can be described as a 5-tuple , where is the set of states, the input alphabet, the transition function, the start state, and the set of accepting states. The machine processes an input string left-to-right by repeatedly updating its current state using . The input is accepted if after the last symbol, the machine is in a state from .
More general variants include NFAs (multiple possible transitions per symbol) and output machines such as Mealy and Moore machines, which are useful when outputs must be generated during processing.
FSM variants: what they base output/next-state on
Conceptual comparison (not a performance benchmark)
Common clarifications (for a “short note” answer)
Knowledge Check
In the standard DFA definition , what does represent?
Explore Related Topics
Write Short Notes on UML Diagrams
Closure Properties of Context-Free Languages (CFLs)
Understanding Digital Counters: Principles, Types, and Applications
Digital counters are sequential circuits built from cascaded flip‑flops that count input events, with a maximum modulus of 2ᴺ for N stages, and are classified as asynchronous (ripple) or synchronous based on clock distribution.
- Asynchronous counters cascade flip‑flop clocks, causing cumulative propagation delay and limiting maximum frequency.
- Synchronous counters receive the clock simultaneously, using combinational logic to eliminate ripple delay and support higher speeds.
- Designing a synchronous Mod‑6 counter involves defining the state sequence, creating excitation tables, simplifying with Karnaugh maps, and wiring JK flip‑flops with derived logic.
- Ring counters yield N states; Johnson counters double this to 2N states.
- Prevent glitches and lock‑out by using Gray‑code sequencing, output strobes, and ensuring unused states redirect to the main count sequence.