Designing a 32K × 32-bit RAM using 128 × 8-bit RAM Chips

To build a larger RAM from smaller RAM chips, you match two dimensions:

1. Depth (number of addressable words) and 2) Width (number of bits per word).

We are given chips of size 128 × 8:

• Each chip contains 128 word locations (depth) and each location is 8 bits wide (width). Memory depth Memory width

We want a target RAM of 32K × 32:

• Depth = 32K words
• Width = 32 bits per word

A common rule for combining RAMs:

• To increase width, connect chips in parallel (same address lines), using chip outputs to form a wider word.
• To increase depth, connect chips in series / via decoding (use additional address bits and chip-select decoding) so only one bank is active for a given address.

The final number of chips is: $\text{chips}=\left(\frac{32\text{ bits}}{8\text{ bits per chip}}\right)\times\left(\frac{32K\text{ words}}{128\text{ words per chip}}\right)$

Key concepts (first used here):

• Chip-select decoding
• Parallel data bus
• Address mapping

Note: This approach assumes standard RAM organization with independent chips that can be placed into width-parallel and depth-decoded banks.

Why $4 \\times 256$ is correct (visual intuition)

A 32-bit word can be split into four 8-bit slices:

• bits $[7:0]$ from chip bank A
• bits $[15:8]$ from chip bank B
• bits $[23:16]$ from chip bank C
• bits $[31:24]$ from chip bank D

So we need 4 chips per word address at a given depth location.

Then, because each chip only holds 128 word addresses, we need 256 such depth locations (decoded using higher address bits), meaning 256 depth banks, each containing 4 chips for width, hence $4 \times 256 = 1024$.