CRC Sender-Side and Receiver-Side Steps (with Worked Examples)
Cyclic Redundancy Check (CRC ) appends a short checksum (the CRC remainder) to the message. The sender computes the remainder using generator polynomial and modulo-2 division. The receiver recomputes and checks whether the remainder indicates an error. The core theory is: treat message bits as a polynomial over GF(2) and divide by to get a remainder. For a properly constructed codeword, the receiver’s final remainder is .2
Key idea (common “append zeros then divide” variant):
- Sender forms such that is divisible by ; then it transmits the last bits as the CRC remainder .
- Receiver divides the received codeword by and checks that the remainder is (if not, an error is detected).2
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩ ↩2
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩ ↩2
-
Cyclic redundancy check - Notes that typical verification can be done by computing the remainder on the received bitstream and checking it equals zero. ↩
CRC sender/receiver intuition (walkthrough)
Essential terminology for the steps
We’ll use a standard CRC setup:
- Let be the generator polynomial with degree (so the CRC remainder has bits).2
- Let be the data bits to protect; interpret them as .
- Use modulo-2 arithmetic: subtract = XOR in the division process.
Useful keywords introduced here:
- generator polynomial
- remainder
- codeword
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩ ↩2
-
Cyclic redundancy check and modulo-2 division (GeeksforGeeks) - Explains generator polynomial/key representation and the role of (degree/remainder bit length). ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
Sender and Receiver CRC workflow
Sender: prepare dividend
1Append zeros to message to create "
Sender: compute CRC
2Modulo-2 divide by to get remainder "
Sender: transmit codeword
3Send (message followed by CRC bits)"
Receiver: recompute remainder
4Divide received bits by "
Receiver: decide
5If remainder is , accept; else detect an error"
Sender-side steps to compute and append CRC
- 1Step 1
Both sides must agree on (the CRC key). The remainder length equals degree of . 2
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Cyclic redundancy check and modulo-2 division (GeeksforGeeks) - Explains generator polynomial/key representation and the role of (degree/remainder bit length). ↩
-
- 2Step 2
Let be degree of . Append zeros to the message bitstring to form the dividend . 2
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
- 3Step 3
Divide the dividend by using modulo-2 (XOR) polynomial division. The degree of ensures the remainder has at most bits; take the remainder . 2
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Cyclic redundancy check - Notes that typical verification can be done by computing the remainder on the received bitstream and checking it equals zero. ↩
-
- 4Step 4
Append the remainder bits to the original message: . Transmit as the codeword.
Footnotes
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
- 5Step 5
If you use a key bitstring for (e.g., 1101 represents ), keep bit ordering consistent during division. 2
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Cyclic redundancy check and modulo-2 division (GeeksforGeeks) - Explains generator polynomial/key representation and the role of (degree/remainder bit length). ↩
-
Receiver-side steps to verify CRC
- 1Step 1
Let the receiver obtain (the transmitted codeword possibly corrupted by channel errors).
Footnotes
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
- 2Step 2
Perform the same modulo-2 division of by .
Footnotes
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
- 3Step 3
If the remainder is , treat the codeword as valid (no detectable error by this CRC). Otherwise, detect an error. 2
Footnotes
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
Cyclic redundancy check - Notes that typical verification can be done by computing the remainder on the received bitstream and checking it equals zero. ↩
-
- 4Step 4
When remainder is , the receiver can discard the last CRC bits and use the earlier bits as the recovered message.
Footnotes
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
-
Worked Example 1: Sender + receiver using (degree ), Data =
We’ll use the common textbook CRC example where (so ) and .
- Degree ⇒ append zeros to the message to form .
- Compute remainder using modulo-2 division to get .
- Transmitted codeword becomes .
Sender-side (explicit steps)
Receiver-side (explicit steps)
Error case illustration (single-bit flip concept)
If the channel flips one bit, the receiver may get something like ; dividing by yields a non-zero remainder, so the receiver detects an error.
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Cyclic Redundancy Check | CRC | Example - Provides the worked example with Data = 100100 and Key 1101, remainder 001, transmitted codeword 100100001, and receiver remainder check (0 for no error). ↩ ↩2 ↩3 ↩4 ↩5 ↩6
Worked Example 2: “Check by re-dividing the received full codeword”
A convenient CRC implementation variant is explicitly described in CRC theory and common practice:
- If you build the transmitted codeword by appending the correct CRC remainder, then the receiver’s remainder check on the full received codeword should be .2
- This avoids needing to “extract CRC and compare two CRC values” in many hardware implementations. Instead, it just performs the division and checks for zero remainder.
This matches the receiver logic: “divide the received bitstring by and check remainder is zero; if so, assume the received message bits are correct.”
Footnotes
-
Cyclic redundancy check - Notes that typical verification can be done by computing the remainder on the received bitstream and checking it equals zero. ↩ ↩2
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
type="tip" title="Pro Tip: Use the “remainder-zeros” property" content="If your sender computes CRC by appending the remainder to the message after dividing (with standard construction), then the receiver can verify by dividing the entire received codeword and checking that the remainder is . This is explicitly described as the typical CRC checking approach."2"
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
type="warning" title="Warning: Division must be modulo-2 (XOR) not integer arithmetic" content="CRC polynomial division operates in GF(2). In modulo-2 division, subtraction equals XOR (no borrows/carries like decimal subtraction). If you use normal integer division/subtraction, you’ll get a wrong remainder and mismatched sender/receiver results."2"
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩
Mini summary table (steps side-by-side)
| Stage | Input | Operation | Output / Decision | Key CRC fact |
|---|---|---|---|---|
| Sender | and | Append zeros; modulo-2 divide | CRC remainder | Remainder has bits where 2 |
| Sender | and | Concatenate | Transmitted codeword | is divisible by (construction) |
| Receiver | and | Divide by | remainder or non-zero | If remainder is , accept; else detect error2 |
Footnotes
-
Cyclic redundancy check - Describes CRC as remainder of polynomial division over GF(2), and typical append-zero/check approach. ↩
-
Cyclic redundancy check and modulo-2 division (GeeksforGeeks) - Explains generator polynomial/key representation and the role of (degree/remainder bit length). ↩
-
Mathematics of cyclic redundancy checks - States the sender’s division form and receiver’s “divide W' by G(x) and check remainder is zero” rule. ↩ ↩2
-
Cyclic redundancy check - Notes that typical verification can be done by computing the remainder on the received bitstream and checking it equals zero. ↩
Common questions about sender/receiver CRC steps
Knowledge Check
In the standard CRC construction, if the generator polynomial degree is , the sender appends how many zeros to the message before division?
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