In the 8051 architecture, registers are central to computation, control, and peripheral interaction. This section focuses on two major groups:

1. Working registers: the eight registers R0-R7, organized into four register banks
2. Special Function Registers (SFRs): memory-mapped control and data registers located in the upper address range 80H-FFH

A clear understanding of these registers is essential because the 8051 uses them for:

• arithmetic and logical operations
• data movement
• bank switching
• interrupt control
• timer/counter operation
• serial communication
• port I/O
• power management
• bit-level manipulation

At a high level, the internal data memory organization relevant to this topic is:

The default working register bank after reset is Bank 0, and the active bank is selected through the RS1 and RS0 bits in the Program Status Word (PSW).

1. The 8 Working Registers: R0-R7

The 8051 provides eight working registers, named:

• R0
• R1
• R2
• R3
• R4
• R5
• R6
• R7

These are the most frequently used registers for temporary data storage and operand handling. They are called working registers because many instructions directly use them as operands.

Examples:

1MOV A, R3      ; copy contents of R3 into accumulator
2ADD A, R2      ; add contents of R2 to A
3MOV R5, #25H   ; load immediate data into R5

However, the 8051 does not implement only one set of R0-R7. Instead, it provides four banks, each containing its own R0-R7. Thus there are actually 32 physical byte locations reserved for working registers in internal RAM.

Register bank layout

So, for example:

• In Bank 0, R0 = 00H, R7 = 07H
• In Bank 1, R0 = 08H, R7 = 0FH
• In Bank 2, R0 = 10H, R7 = 17H
• In Bank 3, R0 = 18H, R7 = 1FH

Only one bank is active at a time.

PSW bank selection encoding

This scheme allows the same instruction, such as MOV A, R0, to refer to different RAM addresses depending on the selected bank.

Why register banks are useful

Register banks provide a fast way to change the processor’s working context without moving data in and out of memory. This is especially valuable in:

• interrupt service routines
• multi-context assembly programs
• time-critical applications

Instead of pushing all working registers onto the stack, an ISR may switch to another bank and use a fresh set of R0-R7.

2. Special Roles of R0 and R1

Although all eight working registers are general-purpose, R0 and R1 have an additional capability: they can be used for register indirect addressing.

Example:

1MOV R0, #40H
2MOV A, @R0

Here, @R0 means that R0 holds a memory address, and the CPU fetches data from that address.

This makes R0 and R1 especially important for pointer-like operations inside internal RAM.

Summary of working register behavior

3. The Accumulator (A Register)

The Accumulator, denoted A or ACC, is the most important CPU register in the 8051. Its SFR address is E0H.

The accumulator is the primary operand and result register for most:

• arithmetic operations
• logical operations
• rotate operations
• data transfer operations

Examples:

1MOV A, #25H
2ADD A, R1
3ANL A, #0FH
4ORL A, R2
5CLR A

In most ALU instructions, one operand is implicitly the accumulator, and the result is also stored back in the accumulator.

Why the Accumulator is special

The 8051 instruction set is designed around the accumulator. Many instructions cannot operate directly between arbitrary memory locations; instead, data often passes through A.

Examples of common patterns:

• MOV A, source
• ADD A, source
• SUBB A, source
• ANL A, source
• ORL A, source
• XRL A, source

Thus, the accumulator acts as the central ALU register.

4. The Program Status Word (PSW)

The Program Status Word (PSW) is an 8-bit SFR located at address D0H. It contains status flags and control bits that describe the current condition of the CPU and help determine arithmetic behavior and register bank selection.

PSW bit layout

Important PSW flags in this module

Carry flag (CY)

The Carry flag is set when an arithmetic operation generates a carry out of the most significant bit in addition, or a borrow condition in subtraction.

It is important for:

• unsigned arithmetic
• multi-byte arithmetic
• Boolean instructions

Auxiliary Carry flag (AC)

The Auxiliary Carry flag indicates a carry from bit 3 to bit 4. It is mainly used in BCD arithmetic.

Overflow flag (OV)

The Overflow flag indicates overflow in signed arithmetic. It helps distinguish whether a result is invalid when numbers are interpreted as signed two’s complement values.

Parity flag (P)

The Parity flag reflects the parity of the accumulator:

• set when A contains an odd number of 1s
• cleared when A contains an even number of 1s

RS1 and RS0

These bits select the active register bank.

Signed vs unsigned arithmetic: CY and OV

A very important concept in the 8051 is that the same binary addition may be interpreted differently depending on whether numbers are considered unsigned or signed.

• CY is mainly used for unsigned overflow
• OV is mainly used for signed overflow

Example 1: Unsigned overflow

Suppose:

$250 + 10 = 260$

An 8-bit register can only hold values from 0 to 255. So 260 cannot fit, and CY is set.

Example 2: Signed overflow

In 8-bit signed representation, values range from:

$-128 \text{ to } +127$

Suppose:

$100 + 40 = 140$

Binary addition produces a bit pattern that does not fit in the signed range, so OV is set.

This dual-flag mechanism allows the 8051 to support both interpretations using the same arithmetic hardware.

5. Special Function Registers (SFRs)

The Special Function Registers are control and data registers mapped into the address range:

$80H \text{ to } FFH$

This region is commonly called the upper 128 bytes of the 8051 address space for internal data memory.

Important points:

• SFRs are memory-mapped
• each SFR has a fixed address and function
• not all addresses in 80H-FFH are used
• in the standard 8051, only a subset of these 128 locations is assigned to actual SFRs

These SFRs control the CPU core and on-chip peripherals.

Major functional categories of SFRs

• CPU and arithmetic registers
• status and pointer registers
• I/O port latches
• timer/counter control and data registers
• serial communication registers
• interrupt registers
• power management registers

6. Common 8051 SFRs and Their Categories

The following table lists the most important SFRs for the standard 8051.

Interpretation by functional group

I/O ports

• P0
• P1
• P2
• P3

Timers/counters

• TCON
• TMOD
• TL0
• TH0
• TL1
• TH1

Serial port

• SCON
• SBUF

Interrupts

• IE
• IP
• interrupt-related bits also appear in TCON

Power management

• PCON

CPU/status

• ACC
• B
• PSW

Pointers

• SP
• DPL
• DPH

7. SFRs Associated with Interrupts, I/O Ports, and Timers/Counters

Interrupt-related SFRs

IE — Interrupt Enable

Located at A8H, this SFR enables or disables interrupts globally and individually.

IP — Interrupt Priority

Located at B8H, this SFR assigns high or low priority to interrupt sources.

TCON — Timer Control / Interrupt Control

Located at 88H, this SFR contains:

• timer run control bits
• timer overflow flags
• external interrupt type/control bits
• external interrupt flags

Thus TCON bridges timer operation and interrupt signaling.

I/O port SFRs

• P0 (80H)
• P1 (90H)
• P2 (A0H)
• P3 (B0H)

Each port latch controls one 8-bit port. These SFRs are bit-addressable, making them highly useful for embedded control.

Timer/Counter SFRs

• TMOD (89H): sets timer operating mode
• TCON (88H): starts/stops timers and reports overflow
• TL0 / TH0: Timer 0 low/high bytes
• TL1 / TH1: Timer 1 low/high bytes

8. Memory Mapping of SFRs in the Upper 128 Bytes

The 8051 separates internal data memory into lower RAM and upper SFR space.

Memory organization relevant to this topic

The phrase “upper 128 bytes” refers to the region 80H-FFH, where SFRs are mapped.

Important clarification:

• This space is not ordinary general-purpose RAM in the standard 8051
• it is reserved for control/status registers
• only defined SFR addresses should be used

9. Bit Addressability in the 8051

One of the most powerful features of the 8051 is its support for direct manipulation of individual bits.

There are two main bit-addressable regions relevant here:

1. Internal RAM locations 20H-2FH
2. Certain SFRs whose addresses end in 0H or 8H

Bit-addressable RAM: 20H-2FH

This region contains 16 bytes, giving:

$16 \times 8 = 128 \text{ bit-addressable bits}$

These bits are assigned bit addresses from 00H to 7FH.

This allows instructions such as:

1SETB 25H
2CLR 25H
3JB 20H, LABEL

This is especially useful for:

• flags
• control states
• Boolean variables
• I/O-oriented logic

Bit-addressable SFRs

In the standard 8051, the important bit-addressable SFRs include:

• P0
• TCON
• P1
• SCON
• P2
• IE
• P3
• IP
• PSW
• ACC
• B

These are bit-addressable because of how the 8051 maps certain SFR addresses and bit fields.

Why bit addressability matters

It enables efficient single-bit instructions:

• SETB bit
• CLR bit
• CPL bit
• JB bit, label
• JNB bit, label

This is one reason the 8051 is well suited for control applications.

10. Conceptual Integration: How These Registers Work Together

The working registers, accumulator, PSW, and SFRs are not isolated topics. They operate together as a coordinated register system.

Example interaction sequence

1. Data is loaded into R0-R7
2. An ALU operation uses the Accumulator A
3. The result updates PSW flags such as CY, AC, OV, and P
4. A decision may be made based on flags
5. The program may then update an I/O port SFR
6. A timer or serial SFR may be configured for peripheral action
7. Interrupt-related SFRs may control asynchronous responses

This makes the 8051 register model highly compact and efficient for embedded control.