Within the 8051 architecture, the stack, Stack Pointer (SP), and Program Counter (PC) are central to understanding how the processor stores temporary information and controls program flow. The stack is a Last-In, First-Out (LIFO) area implemented inside internal RAM, while the SP is an 8-bit register that tracks the current top of the stack. After RESET, the SP initializes to 07H, which means the first byte pushed onto the stack is stored at 08H.2

The Program Counter (PC) is a 16-bit register that holds the address of the next instruction to fetch from program memory.2 During normal sequential execution, the PC advances by the number of bytes in the current instruction—commonly 1, 2, or 3 bytes in the 8051 instruction set.2 During subroutine calls such as LCALL, the CPU saves the return address on the stack and loads the PC with the subroutine address; during RET, the saved address is popped back into the PC so execution resumes after the call.2

These mechanisms are essential for tracing function calls, interrupts, nested routines, and overall control flow in embedded systems.2

Footnotes

1. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³

2. 8051 Microcontroller Architecture Notes - Explains SP width, reset value 07H, and default first stack location 08H. ↩

3. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³

4. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩ ↩²

5. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩

1. The Stack in 8051 Internal RAM

The 8051 stack is not in a separate hardware memory region; it is formed inside internal data RAM. Since the SP reset value is 07H, the location 08H becomes the first stack location by default.2 This matters because lower internal RAM addresses 00H–1FH are also used for register banks, so careless stack growth can overwrite register-bank or other important RAM contents.2

The stack is used to store:

• temporary register contents during software routines,
• return addresses during subroutine calls,
• return addresses during interrupt servicing,
• and any software-managed local data placed there by the programmer.

In conceptual terms, the SP points to the last used stack location.2 Therefore, a PUSH must first move SP to the next free byte, while a POP must read the current top byte before reducing SP.2

Footnotes

1. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³ ↩⁴ ↩⁵

2. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³

3. 8051 Microcontroller Architecture Notes - Explains SP width, reset value 07H, and default first stack location 08H. ↩ ↩² ↩³

4. Intel 8051 Overview (Wikipedia PDF mirror) - Summarizes register-bank mapping and notes the PC as a distinct 16-bit register. ↩

5. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩

2. The Stack Pointer (SP) Register

The Stack Pointer is an 8-bit register, so it can address internal RAM locations in the range 00H to FFH depending on the specific 8051-family device and implemented RAM organization.2 In the classic 8051 core, the stack is associated with on-chip RAM and grows upward.

After RESET:

$$SP = 07H$$

Therefore:

$$\text{First stack write address} = 08H$$

This default is convenient because addresses 00H–07H correspond to Register Bank 0, the default register bank after reset. However, since addresses 08H–1FH overlap other register-bank storage locations, leaving the stack at the default region can be risky in applications that switch register banks or use nested subroutines and interrupts.2

A common embedded programming practice is to relocate the stack to a safer area of internal RAM early in initialization.

Footnotes

1. 8051 Microcontroller Architecture Notes - Explains SP width, reset value 07H, and default first stack location 08H. ↩ ↩² ↩³ ↩⁴

2. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶

3. Intel 8051 Overview (Wikipedia PDF mirror) - Summarizes register-bank mapping and notes the PC as a distinct 16-bit register. ↩ ↩²

4. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³

5. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩

3. The Program Counter (PC)

The Program Counter in the 8051 is a 16-bit register that contains the address of the next instruction to be fetched from program memory.2 Because it is 16 bits wide, the processor can address up to:

$$2^{16} = 65536 \text{ bytes} = 64\text{ KB}$$

of program memory.2

Unlike most other 8051 registers, the PC is not memory-mapped as a normal internal RAM location or SFR accessible by standard data-move instructions. Its primary role is instruction sequencing:

• fetch next opcode from the address in PC,
• increment according to instruction size during normal flow,2
• load a new address on jumps and calls,2
• restore a saved address on RET or RETI.2

For example:

• NOP is 1 byte, so PC usually increases by 1.
• SJMP rel is 2 bytes, so the target is computed relative to PC + 2.
• LJMP addr16 is 3 bytes, and loads the PC directly with the 16-bit destination address.2
• LCALL addr16 first forms the return address as PC + 3, pushes it, then loads PC with the target subroutine address.2

This byte-sensitive behavior is vital when tracing embedded code manually.

Footnotes

1. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³

2. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩ ↩² ↩³

3. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶

4. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩ ↩² ↩³ ↩⁴ ↩⁵

5. Keil Intel MCS-51 Instruction Set - Provides RET/POP semantics and examples of restoring PC from the stack. ↩

4. Tracing SP and PC During LCALL and RET

The most important interaction between SP and PC happens during subroutine calls.

For LCALL addr16, the 8051 performs the following official sequence:2

1. Computes the return address as the address of the next instruction, so:

$$PC \leftarrow PC + 3$$

2. Increments SP and stores the low byte of that return address.
3. Increments SP again and stores the high byte of that return address.
4. Loads PC with the 16-bit subroutine address.2

For RET, the reverse occurs:2

1. The high-order and low-order bytes of the PC are popped successively from the stack according to the hardware-defined sequence.2
2. SP is decremented by 2 overall.2
3. Execution resumes at the restored return address, which is normally the instruction immediately after the original LCALL or ACALL.2

A canonical example from the 8051 instruction documentation states that if initially SP = 07H and LCALL SUBRTN is executed from address 0123H, then the return address becomes 0126H; after the call, SP = 09H, RAM locations 08H and 09H contain the saved return bytes, and PC = SUBRTN.

Footnotes

1. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷ ↩⁸ ↩⁹

2. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩ ↩²

3. Keil Intel MCS-51 Instruction Set - Provides RET/POP semantics and examples of restoring PC from the stack. ↩ ↩² ↩³ ↩⁴

5. PC Behavior for Sequential Flow, Jumps, and Calls

A strong understanding of the PC requires distinguishing between sequential flow and control transfer.

Sequential flow

If the instruction does not change control flow, then:

$$PC_{\text{new}} = PC_{\text{old}} + \text{instruction length}$$

Typical examples:2

• 1-byte: NOP, INC A
• 2-byte: MOV A,#data, SJMP rel
• 3-byte: LJMP addr16, LCALL addr16

Jump instructions

Jump instructions directly modify the PC:2

• SJMP: relative jump from PC + 2
• AJMP: 11-bit absolute jump within the same 2 KB page
• LJMP: full 16-bit absolute jump anywhere in 64 KB
• JMP @A+DPTR: computed jump using accumulator and DPTR

Call instructions

Call instructions also change PC, but unlike jumps they save the return address on the stack first.2

• ACALL: saves return address, jumps within 2 KB page
• LCALL: saves return address, jumps anywhere in 64 KB

Return instructions

• RET: restores PC from the stack after a subroutine.2
• RETI: restores PC from the stack after interrupt servicing and re-enables appropriate interrupt handling logic.2

This distinction explains why subroutines require stack space while ordinary jumps do not.

Footnotes

1. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³ ↩⁴

2. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩ ↩² ↩³

3. Keil Intel MCS-51 Instruction Set - Provides RET/POP semantics and examples of restoring PC from the stack. ↩ ↩²

4. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩

6. Relationship Between SP and PC in Embedded Program Flow

The SP and PC work together most clearly in nested subroutine execution. Each call creates a new stack frame in the simple 8051 sense: not a high-level language frame with automatic locals, but at minimum a stored return address.2 If a subroutine calls another subroutine, another return address is stacked above the first. Because the stack is LIFO, returns occur in the reverse order of calls.

For example:

• Main calls SUB1 → return address for Main is pushed.
• SUB1 calls SUB2 → return address for SUB1 is pushed above it.
• SUB2 executes RET → PC restored to the instruction after the call in SUB1.2
• SUB1 executes RET → PC restored to the instruction after the call in Main.2

This structure is the basis of software modularity in embedded systems.

At each deeper call level:

• PC moves to the next routine to execute,2
• SP rises as return addresses accumulate on the stack.2

If stack usage is not controlled, nested calls plus interrupts plus register saving can overflow available RAM.2

Footnotes

1. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³ ↩⁴ ↩⁵ ↩⁶ ↩⁷

2. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³

3. Keil Intel MCS-51 Instruction Set - Provides RET/POP semantics and examples of restoring PC from the stack. ↩ ↩²

4. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩

5. Intel 8051 Overview (Wikipedia PDF mirror) - Summarizes register-bank mapping and notes the PC as a distinct 16-bit register. ↩

7. Summary

In the 8051:

• The stack is stored in internal RAM and grows upward.
• The SP is an 8-bit register initialized to 07H after RESET, making 08H the first default stack location.2
• PUSH uses pre-increment of SP; POP uses post-decrement.2
• The PC is a 16-bit register that points to the next instruction in program memory.2
• During normal execution, PC typically advances by 1, 2, or 3 bytes, depending on instruction length.2
• During LCALL, the return address is pushed to the stack and PC is loaded with the subroutine address.
• During RET, the saved return address is restored from the stack into the PC.2

Mastering these two registers together allows accurate tracing of subroutines, jumps, interrupt entry/exit, and nested call behavior in 8051-based embedded applications.2

Footnotes

1. Intel MCS-51 User's Manual - Official architecture reference covering internal RAM, upward-growing stack, and program/data memory organization. ↩ ↩² ↩³ ↩⁴

2. Microchip 8051 Instruction Set Manual - Instruction-level definitions for PUSH, POP, LCALL, RET, LJMP, and PC/SP behavior. ↩ ↩² ↩³ ↩⁴ ↩⁵

3. 8051 Microcontroller Architecture Notes - Explains SP width, reset value 07H, and default first stack location 08H. ↩

4. MCS-51 Microcontroller Family User's Manual - Describes PC handling during interrupts and notes that PC is automatically pushed for interrupt service. ↩ ↩²

5. 8051 Instruction Set Reference - Clear descriptions of instruction sizes and PC effects for LCALL, ACALL, AJMP, LJMP, and related control-flow instructions. ↩

6. Keil Intel MCS-51 Instruction Set - Provides RET/POP semantics and examples of restoring PC from the stack. ↩