Logical Instructions

1 hour

Learning Goals

Understand logical AND operation: ANL A, 0FH instruction masks accumulator to lower 4 bits (0x0F = 0000 1111), keeping only specified bit positions and zeroing others, demonstrating bit masking for extracting subfields from bytes
Master logical OR operation: ORL A, 03H instruction sets specified bit positions (0x03 = 0000 0011), combining bits from accumulator with operand pattern, useful for setting specific status flags or combining data structures
Analyze logical XOR operation: XRL A, A instruction (exclusive OR accumulator with itself) always produces 0 result, affecting only parity flag (P) which becomes clear (0), utilizing this pattern for efficient accumulator clearing without affecting other flags
Understand complement instruction behavior: CPL (complement accumulator) flips all bits in accumulator without affecting any flags (CY, AC, OV, P remain unchanged), distinguishing single-operand CPL from two-operand logical operations
Explain CLR and SETB flag behavior: CLR clearing and SETB setting the carry flag without affecting accumulator or other register contents, providing efficient flag manipulation for program control flow
Apply logical instructions to bit masking patterns: using AND to extract bit fields (MOV A, #0FH followed by ANL), using OR to set specific bits, using XOR to toggle or invert patterns, and combining operations for complex bit manipulations
Trace logical instruction execution: analyzing MOV A, #54H followed by XRL A, A demonstrating automatic zero result, recognizing parity calculation in XOR operations (odd number of 1s sets P to 1), and predicting instruction outcomes
Understand conditional logic implementation: using logical operations as alternatives to branch instructions, implementing decision logic through bit patterns, and optimizing control flow for embedded systems without excessive branching

Logical operations form the cornerstone of low-level data manipulation, hardware interfacing, and system control in embedded microprocessors. In the 8051 architecture, Logical Instructions operate at the byte or individual bit level, enabling precise control over memory-mapped registers, input/output ports, and status flags .

A unique and crucial architectural feature of the 8051 is its flag behavior during logical operations. Unlike arithmetic operations (such as ADD or SUBB), byte-level logical instructions (like ANL, ORL, and XRL) do not affect the Carry (CY), Auxiliary Carry (AC), or Overflow (OV) flags in the Program Status Word (PSW) .

However, the Parity Flag (P) is a hardware-driven flag that dynamically monitors the Accumulator (A) . Any instruction that alters the contents of the Accumulator—including all byte-level logical operations—will automatically cause the hardware to re-evaluate the parity of the value inside the Accumulator:

If the number of $1$ bits is odd, $P = 1$ .
If the number of $1$ bits is even (including zero $1$ bits), $P = 0$ .

The diagram below illustrates the flow of a logical instruction through the Arithmetic Logic Unit (ALU) to the Accumulator and its subsequent effect on the PSW:

Logical Instructions of 8051 Microcontroller Guide - Provides an overview of AND, OR, XOR, and Complement operations with registers. ↩ ↩²
8051 Assembly Language Programming & Architectures - Comprehensive guide on register interactions and CPU execution timings. ↩

Logical Instructions of 8051 Microcontroller

Walkthrough of Bit Masking and Bitwise Extraction

1
Step 1
Begin by loading a test byte into the Accumulator. For instance, MOV A, #54H loads the binary value 0101 0100 into A. At this stage, the hardware evaluates the parity of A (two '1' bits, which is even), setting $P = 0$ .
2
Step 2
Apply the logical AND operation using the instruction ANL A, #0FH. The immediate mask value 0FH represents 0000 1111. The ALU performs the bitwise AND: $\text{Accumulator (A): } 0101\ 0100_2$ $\text{Mask (\#0FH): } 0000\ 1111_2$ $\text{Result: } 0000\ 0100_2\ (04H)$ This operation zeroes out the upper four bits while preserving the lower four bits .

Footnotes

Logical Instructions of 8051 Microcontroller Guide - Provides an overview of AND, OR, XOR, and Complement operations with registers. ↩
3
Step 3
Use the logical OR operation ORL A, #03H to set specific bits. The immediate mask 03H (0000 0011) will force the lower two bits of the Accumulator to $1$ , while preserving the remaining bits: $\text{Accumulator (A): } 0000\ 0100_2$ $\text{Mask (\#03H): } 0000\ 0011_2$ $\text{Result: } 0000\ 0111_2\ (07H)$ This is commonly used in driver development to enable specific channels or flags .

Footnotes

Arithmetic and Logical Operations of 8051 - Highlights practical implementation steps for Keil-based micro-assembly environments. ↩
4
Step 4
Execute the single-operand complement instruction CPL A. This performs a bitwise logical NOT operation, flipping every bit in the Accumulator: $\text{Accumulator (A): } 0000\ 0111_2$ $\text{Result of CPL: } 1111\ 1000_2\ (F8H)$ This operation does not affect the carry flag ( $CY$ ), auxiliary carry ( $AC$ ), or overflow ( $OV$ ), but updates $P$ to $1$ because there are now five '1' bits (odd parity) .

Footnotes

Logical Instructions of 8051 Microcontroller Guide - Provides an overview of AND, OR, XOR, and Complement operations with registers. ↩

The XRL Accumulator Clearing Trick

Executing XRL A, A is a highly efficient way to clear the Accumulator to 00H. Because any value exclusive-ORed with itself yields zero, this operation guarantees a result of 00H. Crucially, this affects only the Parity flag (which becomes 0 due to zero '1' bits), leaving the Carry ( $CY$ ), Auxiliary Carry ( $AC$ ), and Overflow ( $OV$ ) flags completely untouched, preserving execution contexts in complex routines .

Logical Instructions of 8051 Microcontroller Guide - Provides an overview of AND, OR, XOR, and Complement operations with registers. ↩

Advanced Bitwise Toggling and Masking Patterns

For developers writing assembly routines, mastering bitwise logical patterns is essential for controlling physical pins and internal states. The three primary two-operand logical operators are defined below:

Instruction	Operation	Common Application	Flag Effects
`ANL destination, source`	Bitwise AND	Bit Masking (forcing specific bits to `0`)	Updates $P$ (if destination is $A$ ). $CY$ , $AC$ , $OV$ unaffected.
`ORL destination, source`	Bitwise OR	Bit Setting (forcing specific bits to `1`)	Updates $P$ (if destination is $A$ ). $CY$ , $AC$ , $OV$ unaffected.
`XRL destination, source`	Bitwise Exclusive-OR	Bit Toggling (inverting select bits) / Clearing	Updates $P$ (if destination is $A$ ). $CY$ , $AC$ , $OV$ unaffected.

Complements vs. Two-Operand Operations

Unlike XRL A, #FFH which requires fetching a 2-byte instruction (opcode + immediate mask data), CPL A is a highly optimized 1-byte, 1-cycle instruction. It performs the logical complement ( $A \leftarrow \bar{A}$ ) completely on-chip within the ALU, bypassing external memory access cycles and conserving code space .

8051 Assembly Language Programming & Architectures - Comprehensive guide on register interactions and CPU execution timings. ↩

1; Objective: If Carry flag (CY) is 1, set Register R0 to A, else set R0 to 0.
2; This classic approach uses jump instructions, creating pipeline bubbles.
3
4    JNC CLEAR_REG     ; 2 cycles: Jump to CLEAR_REG if CY = 0
5    MOV R0, A         ; 1 cycle: Copy Accumulator to R0
6    SJMP CONTINUE     ; 2 cycles: Jump over the else-clause
7CLEAR_REG:
8    MOV R0, #00H      ; 1 cycle: Clear R0
9CONTINUE:
10    ; Execution continues

Direct Bit Manipulation Safety

Be careful when using instructions like CLR C or SETB C. These target the Carry flag in the PSW directly without affecting the Accumulator or other registers. However, when performing logical operations directly on bit-addressable SFRs (such as ANL C, P1.0), the system executes a Read-Modify-Write cycle, which reads the physical state of the pin rather than the output latch, potentially leading to race conditions.

Instruction Performance Metrics

Code size (bytes) vs. Execution Cycles on standard 8051