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Microprocessor

I2C Protocol and Interfacing

1.5 hours

Learning Goals

  • Understand I2C multi-master architecture: recognizing support for multiple master devices on same bus, implementing arbitration for collision resolution when multiple masters transmit simultaneously, enabling flexible network topologies vs single-master SPI
  • Master I2C bus structure: recognizing only two lines (SCL and SDA) for bidirectional communication, utilizing open-drain drivers with external pull-up resistors, allowing any device to pull line low (wired-AND logic), and enabling bus arbitration through pull-down observation
  • Analyze I2C addressing: recognizing 7-bit or 10-bit slave addresses for device identification, understanding address frame transmission with read/write bit (bit 0 indicating transmission direction), and managing address ACK for addressed slave communication
  • Explain I2C data transfer protocol: start condition (SDA high-to-low transition with SCL high), data bit transmission (SCL clock enabling data sampling), ACK/NACK response (receiving device pulling SDA low for ACK or releasing for NACK), and stop condition (SCL high-to-low transition with SDA low)
  • Understand arbitration and collision resolution: recognizing bit-level arbitration when multiple masters attempt simultaneous transmission, examining bus state through pull-up interaction, allowing non-arbitrating masters to retry after bus release
  • Master timing constraints: analyzing SCL frequency specifications (standard 100 kHz, fast 400 kHz, fast-plus 1 MHz modes), calculating data setup/hold times relative to SCL edges, and ensuring proper timing for reliable reception
  • Apply clock stretching: recognizing slave capability to hold SCL low extending bit period for processing delays, allowing flexible device inclusion with varying processing speeds, and managing timeout mechanisms for bus lockup prevention
  • Implement 8051 I2C interfacing: utilizing I2C peripheral if available or implementing bit-banging through GPIO ports, managing start/stop condition generation, implementing master transmitter/receiver and slave modes, and coordinating multi-master arbitration

The Inter-Integrated Circuit (I2C) protocol is a synchronous, multi-master, multi-slave, packet-switched, single-ended, serial communication bus invented by Philips Semiconductors (now NXP) in 1980 . Designed for short-distance communication between integrated circuits on the same board, it minimizes pin count by using only two bidirectional lines: SDA (Serial Data) and SCL (Serial Clock) .

Physical Layer and Wired-AND Logic

Unlike SPI, which uses push-pull drivers, I2C utilizes open-drain (or open-collector) drivers. This means a device can only pull a line to ground (Logic 0) or leave it in a high-impedance state (floating). External pull-up resistors are required to bring the bus to Logic 1 when no device is active . This configuration creates a Wired-AND logic:

  • If any device pulls the line Low, the entire bus becomes Low.
  • The bus only becomes High if all devices release the line.

This physical structure is the foundation for features like multi-master arbitration and clock stretching .

Footnotes

  1. Wikipedia - I2C - Comprehensive history and technical specification of the Inter-Integrated Circuit bus. ↩

  2. Total Phase - 7-bit and 10-bit Addressing - Detailed breakdown of I2C addressing modes. ↩

  3. Analog Devices - I2C Primer - Explanation of open-drain outputs and pull-up resistors. ↩

  4. EEVblog - Bus Arbitration Process - Discussion on how Wired-AND logic facilitates arbitration. ↩

I2C Protocol Explained: Basics, Interface, Clock Stretching, and Communication

Multi-Master Architecture and Arbitration

I2C supports multi-master configurations where multiple devices can initiate a bus transaction. To prevent data corruption during simultaneous transmissions, I2C employs a bit-level arbitration mechanism .

  1. Collision Detection: While transmitting, a master monitors the SDA line.
  2. Arbitration Process: If a master attempts to send a '1' (by releasing the bus) but detects a '0' (because another master is pulling it low), it immediately realizes it has lost arbitration .
  3. Resolution: The losing master stops transmitting and switches to slave mode to see if it is being addressed. The winning master continues its transmission without any data loss or bus contention issues.

This allows for flexible network topologies where multiple microprocessors can share the same peripherals .

Footnotes

  1. EEVblog - Bus Arbitration Process - Discussion on how Wired-AND logic facilitates arbitration. ↩

  2. Aticleworld - I2C Protocol and Interface - Overview of I2C bus architecture and half-duplex nature. ↩

  3. Wikipedia - I2C - Comprehensive history and technical specification of the Inter-Integrated Circuit bus. ↩

I2C Speed Modes and SCL Frequency

Comparison of data transfer rates across different I2C standards

I2C Data Transfer Protocol

  1. 1
    Step 1

    The master initiates communication by pulling SDA from High to Low while SCL remains High. This signals all slaves to listen .

    Footnotes

    1. Design Reuse - I2C Timing Specifications - Analysis of Start/Stop conditions and frequency modes. ↩

  2. 2
    Step 2

    The master sends a 7-bit or 10-bit slave address followed by a Read/Write bit (00 for Write, 11 for Read). Total 8 bits for 7-bit addressing .

    Footnotes

    1. Total Phase - 7-bit and 10-bit Addressing - Detailed breakdown of I2C addressing modes. ↩

  3. 3
    Step 3

    The addressed slave responds by pulling SDA Low during the 9th SCL clock pulse. If SDA remains High, it is a NACK (Not Acknowledge) .

    Footnotes

    1. Wikipedia - I2C - Comprehensive history and technical specification of the Inter-Integrated Circuit bus. ↩

  4. 4
    Step 4

    Data is transferred in 8-bit bytes. After each byte, the receiver must send an ACK bit to confirm receipt.

  5. 5
    Step 5

    Communication ends when the master pulls SDA from Low to High while SCL is High, releasing the bus .

    Footnotes

    1. Design Reuse - I2C Timing Specifications - Analysis of Start/Stop conditions and frequency modes. ↩

Modern 8051 variants (like those from Silabs or NXP) often include a dedicated I2C/SMBus peripheral.

1// Example: Initializing Hardware I2C on 8051 variant
2void I2C_Init() {
3    SMB0CF = 0x80; // Enable SMBus, set clock source
4    SMB0CN = 0x40; // Enable Master mode
5}

Choosing Pull-up Resistors

The value of pull-up resistors (RpR_p) depends on the bus capacitance and speed. For a standard 100 kHz bus, 4.7 kΩ4.7\text{ k}\Omega to 10 kΩ10\text{ k}\Omega is typical. Faster speeds or higher bus loads require lower resistance (e.g., 2.2 kΩ2.2\text{ k}\Omega) to ensure faster rise times .

Footnotes

  1. Analog Devices - I2C Primer - Explanation of open-drain outputs and pull-up resistors. ↩

Clock Stretching Pitfalls

While clock stretching allows slow slaves to pause the master, it can lead to bus lockups if a slave holds SCL low indefinitely due to a crash. Always implement a software timeout in your master driver to recover from such hangs .

Footnotes

  1. STM32 I2C Product Training - Technical details on clock stretching and peripheral support. ↩

Advanced I2C Features

Knowledge Check

Question 1 of 4
Q1Single choice

What physical configuration allows I2C to perform multi-master arbitration without damaging hardware?

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