In the Fundamentals of Microprocessors module, 8-bit architecture is best understood through the Intel 8085, a canonical educational microprocessor. The 8085 is called an 8-bit microprocessor because its arithmetic and logic operations are primarily performed on 8-bit data, while it still uses a 16-bit address bus to access memory. This combination allows it to process one byte at a time while addressing up to:

$2^{16} = 65{,}536 \text{ memory locations} = 64 \text{ KB}$

At a system level, the 8085 integrates the essential CPU subsystems expected in a classical microprocessor:

• Arithmetic Logic Unit (ALU) for arithmetic and logical operations
• Control Unit / Timing & Control for sequencing and signal generation
• Register set for temporary data and address handling
• Bus organization for communication with memory and I/O
• Instruction register and decoder for operation interpretation
• Clock and reset circuitry for synchronized execution and initialization

A useful way to visualize the internal organization is:

The 8085 is typically described as following a Von Neumann model, where instructions and data share the same memory space and bus system. This makes the architecture simpler and cheaper, but it also creates a bottleneck because instruction fetch and data transfer cannot occur fully independently in the same way as in Harvard-style systems.

This section explains the internal architecture, working registers and flags, register pairing, memory addressing hierarchy, control signals such as ALE, timing behavior across T-states, the fetch-decode-execute cycle, and the practical strengths and limitations of 8-bit systems in embedded applications.

1. Core Architectural Blocks of an 8-bit Microprocessor

The internal architecture of an 8-bit microprocessor can be divided into four major functional domains:

CPU datapath

This includes:

• Accumulator
• Temporary internal registers
• General-purpose registers
• ALU
• Flag register

These elements perform the actual data manipulation.

Control path

This includes:

• Instruction Register (IR)
• Instruction Decoder
• Timing and Control Unit

These units determine what operation is to be performed and when signals must be asserted.

Address and data movement path

This includes:

• Program Counter (PC)
• Stack Pointer (SP)
• Address bus
• Data bus
• Address/data multiplexed lower bus lines

These units move instructions and data between CPU, memory, and peripherals.

System interface logic

This includes:

• Clock generator input/interface
• Reset inputs and outputs
• Control/status signals
• Interrupt control
• Serial I/O lines

2. ALU: Computational Heart of the 8085

The Arithmetic Logic Unit (ALU) performs operations such as:

• Addition
• Subtraction
• Increment / decrement
• AND, OR, XOR
• Compare
• Complement
• Rotate / shift-like bit manipulations through instruction support

The ALU usually takes one operand from the Accumulator (A) and another from:

• a general register,
• a memory location addressed through HL,
• or immediate data.

The result is generally stored back in the Accumulator, and status is reflected in the flag register.

3. Control Unit and Timing Logic

The control unit coordinates the fetching, decoding, and execution of instructions. It:

• decodes the opcode,
• determines the required machine cycles,
• generates external control signals like RD̅, WR̅, IO/M̅, and ALE,
• synchronizes all operations with the system clock.

Without the control unit, the ALU and registers would have no orderly execution sequence.

4. Bus Organization

The 8085 uses:

• 8-bit data bus
• 16-bit address bus
• control bus for signals such as read, write, and status

A notable design feature is that the lower address byte and data share the same physical lines:

• AD0–AD7 carry A0–A7 during the early part of a machine cycle
• the same lines later carry D0–D7 for actual data transfer

This is called bus multiplexing.

This multiplexing reduces pin count, which was important in 40-pin microprocessor packaging.

Register Organization in the 8085

The 8085 register set contains both 8-bit working registers and 16-bit special-purpose registers.

A. Accumulator

The Accumulator (A) is the central register used by the ALU. Most arithmetic and logical instructions use it implicitly.

B. General-purpose registers

The 8085 provides six 8-bit general-purpose registers:

• B
• C
• D
• E
• H
• L

These can hold temporary data during program execution.

C. Register pairs for 16-bit work

The 8-bit registers can be combined into three register pairs:

• BC
• DE
• HL

Each pair behaves as a 16-bit register for operations such as:

• holding 16-bit data,
• storing memory addresses,
• acting as counters,
• indirect addressing.

The HL pair is especially important because it frequently serves as a memory pointer. In many instructions, the notation M means “the memory content pointed to by HL.”

D. Special-purpose 16-bit registers

• Program Counter (PC): holds the address of the next instruction
• Stack Pointer (SP): points to the top of the stack in memory

Register Summary Table

Register Pairing Example

If:

• H = 20H
• L = 05H

then the pair HL = 2005H, which can be used as a 16-bit memory address.

This means:

• H stores the high-order byte
• L stores the low-order byte

That hierarchical interpretation is central to understanding 16-bit addressing in an 8-bit CPU.

The Five Flags in the 8085

The 8085 has exactly five active condition flags:

1. Sign (S)
2. Zero (Z)
3. Auxiliary Carry (AC)
4. Parity (P)
5. Carry (CY)

These flags are updated after many arithmetic and logical operations and are used by conditional branch instructions.

Interpretation Notes

• Sign flag reflects the MSB of the 8-bit result. In signed interpretation, MSB = 1 indicates negative.
• Zero flag is important for loop termination and equality checks.
• Auxiliary Carry is especially relevant for BCD arithmetic.
• Parity flag helps detect even parity in data.
• Carry flag supports multi-byte arithmetic and conditional flow control.

Example

Suppose:

$25_{H} + DB_{H} = 100_{H}$

In 8-bit arithmetic, only the lower 8 bits remain in the accumulator:

• Result in A = 00H
• CY = 1
• Z = 1

Thus the processor knows the 8-bit result wrapped around, but also that an overflow carry occurred.

Machine Cycles, T-States, and ALE Timing

A machine cycle is a basic bus-level operation such as:

• opcode fetch,
• memory read,
• memory write,
• I/O read,
• I/O write.

Each machine cycle is divided into T-states (clock periods), such as T1, T2, T3, and possibly more.

Critical ALE behavior

A required timing fact for 8085 is:

• ALE becomes high during T1
• ALE remains low from T2 onward

This behavior is essential because the low-order address is available only temporarily on multiplexed lines. External latches capture that address during T1 while ALE is high.

Why ALE matters

Since AD0–AD7 serve two purposes:

1. low-order address in T1
2. data bus after T1

the system needs a clean separation mechanism. ALE provides that synchronization.

Typical opcode fetch timing concept

General timing interpretation

• T1: address placed on bus, ALE high
• T2: control signals active, data direction established
• T3: data sampled or written
• Additional T-states may occur depending on instruction complexity and wait states

Instruction timing diagrams

Instruction timing diagrams show:

• when addresses become valid,
• when ALE pulses,
• when RD̅ or WR̅ are active,
• when data appears on the bus,
• how many T-states are consumed.

These diagrams are indispensable for:

• hardware interfacing,
• memory design,
• troubleshooting bus behavior,
• understanding processor speed limits.

Clock Circuit and Reset Circuit

A microprocessor cannot operate meaningfully without:

1. a clock source for synchronization
2. a reset mechanism for initialization

1. Clock circuit

The clock determines the pacing of all internal and external operations. In the 8085, timing and control functions are synchronized to the clock, and each T-state corresponds to one clock period.

The clock is essential because it:

• sequences bus activity,
• determines instruction timing,
• synchronizes memory and I/O access,
• ensures repeatable digital operation.

If the clock is too fast for memory or peripherals, the system may require wait states or faster interfacing hardware.

2. Reset circuit

The reset mechanism initializes the microprocessor into a known starting condition. During reset, the processor clears or initializes internal state so that program execution can begin deterministically.

Conceptually, reset:

• places the CPU in a known state,
• initializes control logic,
• prepares the program execution starting point,
• ensures that execution does not begin from random memory activity

A reset circuit is necessary:

• at power-up,
• after faults,
• during system restart,
• during debugging and controlled reinitialization

System importance

Without a valid clock, the CPU cannot sequence operations.
Without reset, the CPU may start in an undefined state.

Von Neumann vs Harvard Architecture

The 8085 is commonly treated as a Von Neumann-style microprocessor in educational comparison because instructions and data are handled through a shared memory organization. In contrast, many modern microcontrollers use Harvard or modified Harvard architecture.

Why this comparison matters

The comparison helps explain why 8-bit classical microprocessors:

• are excellent for learning architecture,
• expose bus timing clearly,
• reveal bottlenecks directly,

while modern microcontrollers:

• optimize throughput,
• separate program and data pathways,
• integrate memory and peripherals more tightly.

Hierarchical Memory Addressing Scheme

Because the 8085 is an 8-bit processor with a 16-bit address bus, memory addressing is naturally hierarchical:

1. Bit level: address lines A0–A15
2. Byte level: one memory location stores one byte
3. Low-order and high-order byte structure: 16-bit addresses are split into upper and lower halves
4. Register-pair addressing: addresses are often formed using paired 8-bit registers
5. Program sequencing level: PC selects instruction bytes in ascending address order unless control flow changes

Memory capacity

The address space is:

$0000_H \text{ to } FFFF_H$

That is:

$65536 \text{ bytes} = 64 \text{ KB}$

Address hierarchy example

Suppose the PC contains:

$2005_H$

Then:

• high-order byte = 20H
• low-order byte = 05H

The processor outputs:

• A15–A8 = 20H
• A7–A0 = 05H during T1 on multiplexed lines

This hierarchical split is the practical reason register pairs and bus multiplexing are so important in 8-bit systems.

Architectural Strengths and Practical Constraints

Strengths

• Simple and readable architecture
• Clear separation of functional blocks
• Good educational value for CPU fundamentals
• Efficient for byte-oriented control tasks
• Hardware interfacing concepts are explicit and visible

Constraints

• Only 8-bit ALU operations natively
• Multi-byte arithmetic requires multiple instructions
• Shared instruction/data organization creates a bottleneck
• Limited memory space relative to modern systems
• More programmer effort is needed for efficient embedded implementations

Embedded application relevance

In embedded systems, architectural understanding directly informs:

• memory mapping,
• timing closure,
• peripheral interfacing,
• control loop behavior,
• interrupt response,
• code size optimization.

For example, when an 8-bit CPU reads a sensor, processes a threshold comparison, and writes to an actuator, the designer must understand:

• how many machine cycles the process needs,
• which flags are affected,
• whether memory or I/O timing is adequate,
• whether bus multiplexing and latching are correctly implemented.